Latency Lead (HFT)

Doghouse Recruitment; Austin (TX); Hybrid; USD 114,000 - 190,000; Full time

Benefits offered by this job

Hybrid work model

Travel ~2 trips/year

Job summary

Doghouse Recruitment's client, a proprietary market maker, is building an Austin latency center and hiring a Lead Latency Engineer to own the vision, measurement, and improvements from the ground up. This founding US role requires hands-on technical leadership across systems, data, and hardware.

You will define baselines, craft a measurable latency roadmap, and drive continuous improvements with developers, infrastructure, and performance teams.

Qualifications

• 5+ years in performance-critical systems, ideally with deep latency ownership.
• Hands-on experience with American exchange connectivity, specifically equities and futures, in the context of latency monitoring and optimization.
• Strong Linux performance tuning and low-latency networking, hands-on enough to specify and validate kernel-bypass and NIC work.
• Solid C++, with hardware-aware instincts (cache hierarchy, false sharing, branch prediction, memory ordering).
• The judgment to read a latency profile, find the real bottleneck, and decide when to tune, when to redesign and when to spend on hardware.
• Comfort working in a matrix rather than a hierarchy: this role has a small management component, mostly guiding others on how to approach latency problems.

Responsibilities

• Build tick-to-trade monitoring essentially from scratch: there is limited monitoring today, no dedicated tooling and no specialized hardware in place, so you will define the baselines the firm measures itself against.
• Turn those findings into a clear latency vision and a prioritized roadmap, with every priority justified by data rather than assumption.
• Drive a continuous stream of measured latency improvements in close collaboration with development, infrastructure and performance: the C++ hot path with development, the network and hardware path (kernel bypass, NIC tuning, colocation) with infrastructure, and measurement and tuning with performance.
• Specify latency requirements for colocation, time-sync, NIC and hot-path changes, and validate their real-world impact with your own measurements.
• Lead latency design reviews for new systems, and raise the wider team's ability to read and act on latency data, treating stakeholders as if they are new to it.
• Scope the case for FPGA and SmartNIC offload on the hottest paths together with hardware specialists; this work has not started yet, and you would be the one to get it moving.
• Work across a stack that blends third-party software, specialized hardware and custom-built components: you don't need to write everything yourself, but you need to understand it deeply enough to develop and configure it.

Skills

Performance-critical systems

Low-latency networking

C++

Linux tuning

Hardware-aware instincts

Latency monitoring

Tools

Kernel bypass

SmartNIC offload

Job description

Our client is a proprietary market maker. In this market, edge is measured in nanoseconds, the gap between a market-data packet arriving and an order leaving the building, but today they don't have visibility into where they actually stand. They're not chasing being the fastest, just fast enough, and the first step is finding out. As they build out their Austin office, they are hiring a Lead Latency Engineer to own that from the ground up: to establish tick-to-trade monitoring where none exists today, set the vision and roadmap the data points to, and drive a continuous stream of measured improvements.

This is a founding role for their US latency capability. You will define what good looks like, build the measurement and tooling to prove it, and grow the discipline across the firm as the team is built out around you. You will not manage headcount, but you will work in a matrix across development, data, infrastructure and performance, and you will need to bring people who don't live in latency every day along with you.

What you'll do

• Build tick-to-trade monitoring essentially from scratch: there is limited monitoring today, no dedicated tooling and no specialized hardware in place, so you will define the baselines the firm measures itself against.
• Turn those findings into a clear latency vision and a prioritized roadmap, with every priority justified by data rather than assumption.
• Drive a continuous stream of measured latency improvements in close collaboration with development, infrastructure and performance: the C++ hot path with development, the network and hardware path (kernel bypass, NIC tuning, colocation) with infrastructure, and measurement and tuning with performance.
• Specify latency requirements for colocation, time-sync, NIC and hot-path changes, and validate their real-world impact with your own measurements.
• Lead latency design reviews for new systems, and raise the wider team's ability to read and act on latency data, treating stakeholders as if they are new to it.
• Scope the case for FPGA and SmartNIC offload on the hottest paths together with hardware specialists; this work has not started yet, and you would be the one to get it moving.
• Work across a stack that blends third-party software, specialized hardware and custom-built components: you don't need to write everything yourself, but you need to understand it deeply enough to develop and configure it.

What you'll bring

• 5+ years in performance-critical systems, ideally with deep latency ownership. This doesn't have to be trading: candidates from HPC or comparable high-performance production environments are welcome, provided they understand what it takes to operate in a latency-critical setting.
• Hands-on experience with American exchange connectivity, specifically equities and futures, in the context of latency monitoring and optimization. Energy markets experience is not relevant here.
• Strong Linux performance tuning and low-latency networking, hands-on enough to specify and validate kernel-bypass and NIC work.
• Solid C++, with hardware-aware instincts (cache hierarchy, false sharing, branch prediction, memory ordering). You should be comfortable enough to build things yourself when needed, without needing to own every line of production code.
• The judgment to read a latency profile, find the real bottleneck, and decide when to tune, when to redesign and when to spend on hardware.
• Comfort working in a matrix rather than a hierarchy: this role has a small management component, mostly guiding others on how to approach latency problems, rather than owning headcount.

Nice to have

• Experience building a latency monitoring capability from zero, rather than scaling an existing one.
• FPGA-based acceleration exposure.
• Familiarity with European exchange connectivity, given the infrastructure you build needs to work globally.
• Open-source or published work on low-latency systems.

Good to know

• You'll report into a future Head of IT Operations, a role that is still being hired. Until then, you report to the current IT lead.
• Working hours run 7:30 AM to 3:30 PM US time; you won't be expected to cover EU hours, but you will work closely with people based there.
• This role is hybrid with 3+ days at the office. Being on site is optional but encouraged for the first few months to ramp up quickly; after that, hybrid flexibility applies.
• The Austin office currently has around 16 people, growing to around 30 by the end of the year.
• Expect roughly two trips per year to the firm's other offices.
• Up to 190K base (with exceptions) + huge bonus component.