Get a reply from this employer — a resume and cover letter tailored to exactly what they’re hiring for.
Kalpa Group in New York seeks a senior C++ systems engineer to own end-to-end HFT execution paths, from order routing to market data and latency tooling. You will design lock-free components, implement kernel bypass networking, and optimize for sub-microsecond paths in Linux.
Operate in a zero-bloat stack with close collaboration to quants and traders; leverage C++20/23, FIX/ITCH interfaces, and high-throughput IPC.
Modern C++ (20/23), High-Frequency Trading (HFT), Kernel Bypass, Lock-Free Architecture
$200,000 – $300,000 Base Salary + Performance Bonus + Benefits (Circa $1M+ Total Comp)
Open to guaranteed first-year bonus structures, sign-on buyouts, and non-compete coverage for exceptional talent.
High-frequency execution in 10-year-old monolithic codebases is exhausting.
At many Tier-1 HFT prop shops and giant multi-managers, 80% of a senior engineer's day is spent navigating C++03 tech debt, fighting template bloat, waiting on risk committees, or building tools three layers removed from live trade execution.
We are partnering with a fast-growing buy-side quantitative trading group rebuilding their core HFT execution, market data, and order-routing architecture across US equities, options, and futures.
This is a clean-slate platform build: zero legacy code debt, zero release-management bureaucracy, and direct, daily proximity to quant research and live desk execution.
We are looking for senior C++ systems engineers who want complete end-to-end architectural ownership of the tick-to-trade path rather than managing a tiny, isolated slice of an engine.
Modern C++ (17/20/23) running on bare-metal, heavily tuned Linux kernels. Custom lock-free ring buffers, shared memory IPC, and kernel bypass networking sit at the absolute core of the high-frequency execution path.
While C++ handles the hot execution path, Python and Rust are used across off-path research tooling, simulation, and platform pipelines.
Experience with FPGA co-design, venue launch expansion, or custom hardware acceleration is a plus, but not required. What matters is strong systems-level engineering judgment and the ability to build reliable, high-performance execution software without overengineering.