Kernel Engineer for High-Performance AI Compute

River AI; Austin (TX); On-site; USD 200,000 - 420,000; Full time

Benefits offered by this job

Health, dental, and vision benefits

Unlimited PTO

Relocation support

Visa sponsorship

Job summary

River AI is building the foundational compute engine for its high-performance silicon in Austin or Palo Alto. You will design kernel generators that emit optimized assembly and push the hardware to its theoretical limits for DL operations like GEMMs and custom activations.

The role requires shipping highly optimized kernels, working with compiler engineers and hardware teams, and optimizing memory and pipelines for maximum throughput.

Qualifications

• Bachelor's degree in a related field with 5+ years of experience in low-level performance programming.
• Strong understanding of hardware programming models and shipped kernels.
• Deep knowledge of computer architecture, vector units, and memory hierarchies.
• Proficiency in modern C++ for meta-programming and code-generation frameworks.

Responsibilities

• Design and build C++ code-generation frameworks that emit optimized ISA assembly for custom silicon.
• Author and optimize core DL primitives (GEMM/MatMul, Attention, Convolutions).
• Tune instruction scheduling, register allocation, and software pipelines.
• Design tiling, double-buffering, and data-m movement for on-chip SRAM.
• Collaborate with RTL/architecture teams to inform ISA and future units.
• Benchmark against hardware simulators and ensure mathematical correctness.

Skills

C++ performance programming

High-performance computing

Low-level software development

Collaborative cross-team work

Mathematics for DL

Education

Bachelor's degree in Computer Engineering/Computer Science/Electrical Engineering

Tools

CUDA

Triton

CUTLASS

Custom accelerator assembly

Job description

River AI is building the foundational compute engine for its high-performance silicon in Austin or Palo Alto. You will design kernel generators that emit optimized assembly and push the hardware to its theoretical limits for DL operations like GEMMs and custom activations.

The role requires shipping highly optimized kernels, working with compiler engineers and hardware teams, and optimizing memory and pipelines for maximum throughput.