Junior ASIC Verification Engineer, Satellite Communications

Amazon Inc.

Sunnyvale (CA)

On-site

USD 115,000 - 160,000

Full time

36 hours ago
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Job summary

Amazon Kuiper Manufacturing Enterprises LLC is seeking a verification engineer to define and implement SOC verification for high-speed wireless communications for LEO satellite systems. You will define test plans, develop regression environments in UVM, and validate ASIC implementations in Verilog/SystemVerilog, collaborating with design and system teams.

The role requires 2+ years in verification and UVM, a BS in Electrical/Communications Eng, and familiarity with Matlab.

Qualifications

  • Bachelor's degree in Electrical or Communications Engineering or related field.
  • 2+ years in verification preferably in communication systems.
  • 2+ years in UVM.

Responsibilities

  • Implement a state of the art verification environment to facilitate testing of the RTL against reference Matlab/C models.
  • Develop detailed test plans and write tests, run regressions, collect coverage matrices and report progress to the program.
  • Participate in the validation of ASIC implementations in Verilog/SystemVerilog.
  • Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM.
  • Develop a highly automated environment to run regressions that can be used to make builds and maintain organization of the database.

Skills

2+ years verification
2+ years in UVM
Strong written and verbal skills

Education

Bachelor's degree in Electrical or Communications Engineering
Master's or Ph.D in Electrical / Communications Engineering

Tools

Matlab
SystemC
C

Job description

Amazon Kuiper Manufacturing Enterprises LLC is seeking a verification engineer to define and implement SOC verification for high-speed wireless communications for LEO satellite systems. You will define test plans, develop regression environments in UVM, and validate ASIC implementations in Verilog/SystemVerilog, collaborating with design and system teams.

The role requires 2+ years in verification and UVM, a BS in Electrical/Communications Eng, and familiarity with Matlab.

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