IP DFT Engineer

PER International; Austin (TX); Hybrid; USD 140,000 - 190,000; Full time

Benefits offered by this job

Performance bonus

Incentive programs

Health coverage

Life and disability insurance

Paid time off

Parental leave

Retirement benefits

Other employee benefits

Job summary

PER International in Austin, TX is seeking an experienced DFT engineer to design and implement test strategies for mixed-signal IP blocks. You will work across analog, digital, verification and integration teams to ensure high test coverage and manufacturability.

You will lead ATPG/diagnosis efforts, develop DFT architectures, and document procedures, while contributing to the evolution of best practices in semiconductor IP testing. Hybrid work model offered.

Qualifications

• Bachelor's or Master's in Electrical/Computer Engineering or related field.
• 7+ years of DFT implementation experience for digital/mixed-signal IP.
• Strong understanding of scan, ATPG, JTAG, test-point insertion and coverage analysis.
• Experience with industry-standard DFT tools: Synopsys DFT Compiler, TetraMax, Tessent, VCS, Verdi.
• Familiarity with RTL design and simulation using Verilog/VHDL.

Responsibilities

• Develop and implement DFT architectures for mixed-signal IP blocks.
• Perform scan insertion and test point insertion for digital portions.
• Develop test enablement strategies for analog/mixed-signal circuitry.
• Collaborate with analog and digital design teams to meet DFT requirements.
• Conduct DFT verification including ATPG, fault simulation and coverage analysis.
• Support scan diagnosis and testability analysis.
• Work with IP integration teams to embed DFT features into subsystems/SoCs.
• Document DFT architecture, verification methods, and test procedures.
• Contribute to continuous improvement of mixed-signal DFT methodologies.

Skills

DFT implementation

ATPG

JTAG

RTL design

Verilog

VHDL

debugging

test coverage analysis

Python

Scripting

Education

Bachelor's or Master's degree in Electrical Engineering

Tools

Synopsys DFT Compiler

TetraMax

Siemens Tessent

VCS

Verdi

Job description

Work Setup: Hybrid – Monday to Thursday onsite, Friday remote

About the Company

Our client is a leading global fabless semiconductor company developing advanced, high-performance and power-efficient technologies for a wide range of connected applications.

The company operates at the forefront of areas including AI, wireless connectivity, mobile and computing technologies, with semiconductor solutions used across consumer electronics, smart devices, automotive, high-performance computing and data center applications. Working with major technology brands worldwide, the business offers engineers the opportunity to contribute to advanced semiconductor technologies used across global markets.

Job Summary

This position will focus on developing and implementing Design for Test (DFT) strategies for mixed-signal IP blocks, ensuring high test coverage, testability, and manufacturability. You will work closely with analog, digital, verification, and integration teams throughout the IP development lifecycle.

Key Responsibilities And Activities Include

• Develop and implement DFT architectures and methodologies for mixed-signal IP blocks.
• Perform scan insertion and test point insertion for digital portions of mixed-signal IP.
• Develop test enablement strategies for analog and mixed-signal circuitry.
• Collaborate with analog and digital design teams to incorporate DFT requirements during IP development.
• Perform DFT verification, including ATPG, fault simulation, fault grading, and coverage analysis.
• Support scan diagnosis and testability analysis.
• Work with integration DFT teams to integrate IP-level DFT features into larger subsystems and SoCs.
• Document DFT architecture, verification methodology, and test procedures.
• Contribute to continuous improvement of mixed-signal DFT methodologies and best practices.

Education And Experience Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related discipline.
• 7+ years of experience in DFT implementation for digital, mixed-signal, or semiconductor IP.
• Strong understanding of DFT concepts including scan/scan insertion, ATPG, JTAG, test point insertion, scan diagnosis, fault simulation/fault grading, and test coverage analysis.
• Experience with industry-standard DFT and simulation tools such as Synopsys DFT Compiler, TetraMax, Siemens Tessent, VCS, or Verdi.
• Familiarity with RTL design and simulation, including Verilog and/or VHDL.
• Understanding of analog or mixed-signal design and test concepts.
• Experience with ATPG, fault grading, and coverage analysis for digital logic.
• Strong analytical, debugging, problem-solving, and communication skills.

Competency requirement

• Silicon debug and production test experience.
• Scripting experience using Python, Perl, and/or Tcl.
• Knowledge of hierarchical DFT and subsystem integration.
• Understanding of low-power design and associated DFT challenges.
• Experience working with mixed-signal semiconductor designs.
• Experience collaborating across multi-site and cross-functional engineering teams.

Competency requirement

The position offers a competitive compensation and benefits package based on the successful candidate’s skills, experience, and qualifications.

The overall package may include a performance bonus, short- and long-term incentive programs, comprehensive health coverage, life and disability insurance, paid time off, parental leave, retirement benefits, and other employee benefits.

• performance bonus
• short- and long-term incentive programs
• comprehensive health coverage
• life and disability insurance
• paid time off
• parental leave
• retirement benefits
• other employee benefits