Implementation Timing / STA Design Engineer

Qualcomm; Santa Clara (CA); On-site; USD 100,000 - 160,000; Full time

Job summary

An established industry player seeks skilled engineers for its SoC Implementation Team, focusing on timing constraints and power analysis for cutting-edge chips. This role offers a chance to work on advanced technologies in mobile, AI, and automotive sectors. Candidates with a strong background in ASIC design and proficiency in tools like Primetime and scripting languages will thrive in this dynamic environment. Join a team that drives innovation and contributes to the development of next-generation experiences, making a significant impact on the future of technology.

Qualifications

• 4+ years of experience in ASIC design, verification, or related fields.
• Proficient in tools for timing analysis and power-aware synthesis.

Responsibilities

• Develop constraints for power-aware synthesis and timing analysis.
• Collaborate with design teams to identify timing requirements.
• Validate clock domain crossing and design constraints.

Skills

Timing Constraints Development

Power Analysis

Static Timing Analysis (STA)

Timing Closure

Scripting (Tcl, Perl, Python)

Education

Bachelor's degree in Science or Engineering

Master's degree in Science or Engineering

PhD in Science or Engineering

Tools

Primetime

Fishtail

TCM

Job description

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.

Qualcomm’s SoC Implementation Team is looking for skilled engineers to focus on timing constraints development, power analysis, STA, and timing closure for premium-tier chips. This is an excellent opportunity to join the Snapdragon implementation team, which is responsible for SoCs in sub-3nm nodes across mobile, AI, and automotive sectors. Candidates should have at least 2 years of experience and be proficient with tools such as Primetime, Fishtail/TCM. Scripting skills in Tcl, Perl, or Python are also desirable.

Job Description: Principal Duties and Responsibilities

1. Develop constraints for physical power-aware synthesis, setup for various modes/corners and low-power multi-voltage domain crossings, and signoff with static timing analysis.
2. Collaborate closely with RTL design and physical design teams to identify timing requirements and bottlenecks.
3. Generate/review, and validate clock domain crossing and design constraints to achieve timing closure of complex SoC cores.
4. Review and integrate HM constraints into SoC and ensure correlation between HM and SoC timing.
5. Analyze timing across modes and corners, understand concepts like path pessimism and margins.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

OR

Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.

OR

PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [e-mail] or call Qualcomm's toll-free number found here (https://qualcomm.service-now.com/hrpublic?id=hr_public_article_view&sysparm_article=KB0039028).