Hybrid Technical Program Manager, Chiplet AI Silicon

Tenstorrent; California; Hybrid; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent seeks an experienced Technical Program Manager to lead the end-to-end software development of a next-generation Chiplet-based SiP, spanning architecture to tape-out, silicon debug, and software productization across AI, CPU, memory, and I/O domains.

The role is hybrid, based in Santa Clara, CA, Austin, TX, or Toronto, ON, with multiple experience levels considered and offers aligned to the chosen level.

Qualifications

• 10+ years of experience in technical program management or chip-level engineering, with 2+ years in multi-chip/chiplet systems.
• Familiar with heterogeneous compute architectures (AI, CPU, memory, networking) and early software phases (architecture, pre-/post-silicon).
• Proven ability to manage 40+ engineer programs, external vendors (PCIe, D2D, Ethernet), and full software stacks from bare-metal to ML frameworks.
• Strong understanding of hardware-software codesign at chiplet, package, and system levels.
• Highly organized, adaptable, and expert in tools like JIRA, Confluence, and fast-paced decision making

Responsibilities

• Devise and manage multi-year software roadmaps and coordinate across silicon, firmware, and runtime teams.
• Define success metrics, drive work breakdown structures, and track progress with strong risk management and alignment strategies.
• Own shift-left strategies to de-risk bring-up and accelerate time-to-market.
• Manage vendor software integrations (PCIe, D2D, Ethernet), and set up robust CI/CD and testing frameworks.
• Communicate clearly with executives, engineers, and stakeholders, balancing transparency with thoughtful tradeoff discussions.

Skills

Program management

Chiplet systems

JIRA

Confluence

Cross-functional leadership

Tools

JIRA

Confluence

Job description

Tenstorrent seeks an experienced Technical Program Manager to lead the end-to-end software development of a next-generation Chiplet-based SiP, spanning architecture to tape-out, silicon debug, and software productization across AI, CPU, memory, and I/O domains.

The role is hybrid, based in Santa Clara, CA, Austin, TX, or Toronto, ON, with multiple experience levels considered and offers aligned to the chosen level.