Hybrid FPGA Design Engineer – DSP & RF/Comms

PeoplePilot; Melbourne (FL); Hybrid; USD 120,000 - 150,000; Full time

Job summary

PeoplePilot seeks a Senior FPGA Design & Development Engineer in Melbourne, Florida for a hybrid role. The position requires 3 days onsite and 2 days work from home, with a compensation of $120,000 - $150,000 per year.

Responsibilities include FPGA design, DSP algorithm implementation, hardware bring-up, lab validation, system integration, and participation in design reviews. Must have Xilinx tools, MATLAB, ModelSim/Questa, and ITAR-compliant status.

Qualifications

• DSP in FPGA hardware implementation.
• Experience with Xilinx FPGA tools and architectures.
• MATLAB modeling and simulation experience.
• Hardware lab testing and system integration experience.
• Timing analysis and timing closure experience.
• RF, SDR, radar, or communications systems experience.
• FPGA board bring-up and hardware debugging experience.
• Experience with ModelSim and Questa.
• Requirements capture and detailed design documentation experience.
• Must be a US Citizen or Green Card holder due to ITAR requirements.

Responsibilities

• FPGA design, development, and documentation.
• DSP algorithm implementation in FPGA hardware and hardware bring-up.
• Debugging, lab validation, and system integration support.
• Participation in design reviews.

Skills

DSP in FPGA

Xilinx tools

MATLAB modeling

Hardware lab testing

Timing analysis

RF/SDR/ radar

FPGA bring-up

ModelSim/Questa

Design documentation

ITAR compliance

Tools

ModelSim/Questa

Xilinx tools

Job description

PeoplePilot seeks a Senior FPGA Design & Development Engineer in Melbourne, Florida for a hybrid role. The position requires 3 days onsite and 2 days work from home, with a compensation of $120,000 - $150,000 per year.

Responsibilities include FPGA design, DSP algorithm implementation, hardware bring-up, lab validation, system integration, and participation in design reviews. Must have Xilinx tools, MATLAB, ModelSim/Questa, and ITAR-compliant status.