High Speed PHY FW Engineer

Cadence Design Systems, Inc.

San Jose (CA)

On-site

USD 102,000 - 189,000

Full time

14 days+
Application generator

Get a reply from this employer — a resume and cover letter tailored to exactly what they’re hiring for.

Get past ATS filters

Job summary

Cadence is seeking a High Speed SERDES PHY Firmware Design Engineer (T1/T2) in the San Jose area. You will join a dynamic team developing firmware for industry-standard high-speed SERDES, from architecture to deployment.

You should have strong C/C++ and Python skills, experience with verification, and the ability to work across product engineering and validation teams to deliver robust IP solutions for silicon designs.

Qualifications

  • Firmware architecture development and feature implementation.
  • Collaborate with verification to debug FW issues in simulations.
  • Post-silicon testing and field issue remediation with FW improvements.

Responsibilities

  • Build system-level prototype control software for SERDES adaptation and control algorithms.
  • Implement FW features and ensure functionality with verification/validation teams.
  • Support validation during electrical/system characterization.
  • Assist product engineering during customer IP deployment.

Skills

C/C++
Python
Wireline comms
Mixed-signal DSP
Problem solving

Education

BSc or MSc in Electrical Engineering

Job description

SAN JOSE

Full time

R55518

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Working COMPANY OVERVIEW

The Future of Intellectual Property is Here

Electronic innovation is everywhere, from smart sensors to smart cities, and it is transforming the way people work, live, and play. Cadence is excited to play a role in this innovation, not only as a world leader in electronic design automation (EDA) for over 25 years, but also as a driving force in the advancement of intellectual property (IP).

Cadence® IP solutions will change the way you think about and use IP in your system-on-chip (SoC) designs. As you use more IP to fortify your SoCs with new functionalities, we can help you reduce the complexity and risk inherent in designing for smart technology while meeting your performance, area, and power (PPA) requirements.

Cadence is the fastest-growing silicon IP provider, with a proven portfolio and many industry firsts in design IP and verification IP. Engineers choose Cadence when they want the best in interface, memory, analog, peripherals, processor, and verification IP.

Our Goal: a Perfect Fit in Your SoC

Cadence provides an open IP platform and IP Factory approach so you can design, customize, and verify IP and IP subsystems to fit your SoCs in ways that weren’t possible before. We work with you to make sure our IP fits as seamlessly as possible into your designs. Growing synergies within our IP portfolio, and between our IP portfolio and EDA tools, provide you with important flexibility and time-to-market advantages over traditional IP integration approaches.

Quality is Integral to What We Do, Not an Afterthought

Cadence has amassed thousands of IP tape outs, and our IP solutions are in use by many of the world’s leading semiconductor and systems companies. The Cadence quality assurance program is based on clear, documented policies and reproducible procedures that begin in product definition and development and extend through testing and release to ongoing maintenance and support. Our procedures include specification and maintenance of appropriately detailed product definitions and test/release plans for every Cadence product.

POSITION DETAILS

High Speed SERDES PHY Firmware Design Engineer (T1/T2)

This is an opportunity to join a dynamic and growing team of experienced engineers developing physical IP for industry-standard high-speed serial-link protocols. The successful candidate will ideally be a highly motivated self-starter who is able to work independently to complete assigned tasks and can also contribute to project leadership. It is expected that the candidate will contribute during all phases of firmware development for high speed SERDES from architecture development to implementation, verification, testing and customer deployment.

This includes:
  • Contribution during firmware architecture development and implementation of the defined firmware features.
  • Working closely with verification team to debug and fix the FW issues found with verification simulations.
  • Involvement during post-silicon testing and validation to identify any FW and HW related functionality and performance issues and implement any necessary FW improvements to address these issues.
  • Interaction with Product Engineering, System Validation and Design team to debug IP issues in the field and provide hot fixes.
Responsibilities include:
  • Help to build system level prototype control software to develop/validate adaptation, equalization, and control algorithms for high speed SERDES.
  • Implement assigned FW features and work closely with verification and validation team to ensure the functionality and robustness of the implemented features.
  • Support of Validation team during electrical and system characterization.
  • Support of Product Engineering team during customer deployment of the IP.
Specific desired skills:
  • Solid programming knowledge in C/C++ and Python
  • Understanding of wireline communication principles
  • Knowledge in mixed signal circuit design and digital signal processing techniques
  • Strong problem solving and communication skills
  • BSc or MSc in Electrical Engineering
  • US Citizen or Permanent resident

The annual salary range for California is $101,500 to $188,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

  • Additional Jobs (https://cadence.wd1.myworkdayjobs.com/addl_jobs)
Equal Employment Opportunity Policy:
  • Read the policy(opens in a new tab) (https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/company/careers/equal-employment-opportunity-policy.pdf)

We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact staffing@cadence.com.

Privacy Policy:

Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) (https://www.cadence.com/en_US/home/privacy/privacy-policy.html) .

E-Verify Cadence participates in the

E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) (https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/company/careers/e-verify-participation-poster.pdf)

Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

High Speed PHY FW Engineer
High Speed PHY FW Engineer

Cadence • San Jose (CA)

On-site
USD 101,500 - 188,500
Sr. Interface IC, IP Sales Executive II
Sr. Interface IC, IP Sales Executive II

Cadence Design Systems, Inc. • San Jose (CA)

On-site
USD 248,000 - 372,000
Sr Principal Engineer -SIPI
Sr Principal Engineer -SIPI

Cadence Design Systems, Inc. • San Jose (CA)

On-site
USD 154,000 - 286,000
401(k) plan with employer match
Employee stock purchase plan
Medical, dental and vision plans
+1
Principal AE, Serdes Design IP
Principal AE, Serdes Design IP

Cadence Design Systems • San Jose (CA)

On-site
USD 127,000 - 237,000
401(k) plan with employer match
Employee stock purchase plan
Medical, dental and vision plans
+1
High Speed Interface Protocols, Sr Application Engineer
High Speed Interface Protocols, Sr Application Engineer

Cadence Design Systems • San Jose (CA)

Hybrid
USD 84,000 - 156,000
401(k) plan with employer match
Employee stock purchase plan
Medical, dental and vision options
+1
Mixed Signal IP - Senior Program Manager
Mixed Signal IP - Senior Program Manager

Cadence Design Systems, Inc. • San Jose (CA)

On-site
USD 118,000 - 218,000
RTL2GDS IC Sr. Principal Design Engineer
RTL2GDS IC Sr. Principal Design Engineer

Cadence Design Systems, Inc. • San Jose (CA)

On-site
USD 161,000 - 299,000
Paid vacation
401(k) with employer match
Employee stock purchase plan
+1
Lead Analog IC Design Engineer
Lead Analog IC Design Engineer

Cadence Design Systems • San Jose (CA)

On-site
USD 119,000 - 221,000
401(k) plan with employer match
Employee stock purchase plan
Medical, dental, and vision plans
+1
Product Engineer (Analog Circuit Design)
Product Engineer (Analog Circuit Design)

Cadence Design Systems, Inc. • San Jose (CA)

On-site
USD 115,000 - 213,000
Bonus
Equity compensation
Benefits (health, 401(k) match)
Lead Software Engineer
Lead Software Engineer

Cadence Design Systems, Inc. • San Jose (CA)

On-site
USD 119,000 - 221,000
Paid vacation
401(k) match
Employee stock purchase plan
+2