High-Speed Interface Validation Engineer, Post Silicon Validation (AWS)

Amazon; Austin (TX); On-site; USD 143,700 - 194,400; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid time off

Parental leave

Job summary

Amazon’s Annapurna Labs unit in Austin seeks a High‑Speed Interface Validation Engineer to validate HBM, PCIe, UCIe and SerDes interfaces from PHY training to production deployment.

You will perform electrical characterization, protocol testing, and stress‑test links under varying conditions while collaborating with PHY teams on equalization and margin improvements.

Qualifications

• Bachelor's degree in CS, CE, or EE or equivalent test automation experience.
• 3+ years of professional software development experience (non-internship).
• 3+ years validating high‑speed interface technologies (HBM, PCIe, DDR, SerDes, or UCIe).
• Experience with RF measurement equipment and SI measurement techniques.

Responsibilities

• Validate high‑speed interfaces end‑to‑end from PHY training through sustained traffic.
• Perform electrical characterization: eye diagrams, jitter analysis, margin assessment.
• Execute protocol‑level compliance testing and interoperability validation against specs.
• Stress‑test links across PVT corners and aging conditions.
• Debug link training failures, bit errors, and performance degradation with lab tools.
• Collaborate with PHY design teams on equalization optimization and silicon feedback.

Skills

Python

MATLAB

Perl

Signal integrity analysis

Eye diagram analysis

Jitter analysis

Voltage margin

Education

Bachelor's degree in CS/CE/EE

Tools

MATLAB

Python

Oscilloscopes

Job description

High-Speed Interface Validation Engineer, Post Silicon Validation

Annapurna Labs, an AWS organization with development centers in the U.S. and Israel, builds custom silicon and software for AWS customers. Our team combines cloud-scale innovation with world-class expertise across silicon engineering, hardware design, verification, software, and operations to tackle technical challenges that have never been seen before.

Join our Post‑Silicon Validation team to validate the critical high‑speed interconnects — HBM, PCIe, UCIe, and chip‑to‑chip links — that enable massive bandwidth and scaling in AWS's next‑generation ML accelerators. You'll ensure link integrity, performance, and reliability at the electrical and protocol layers across the full product lifecycle, from first silicon through production deployment in AWS data centers.

You’ll work in a fast‑paced, startup‑like environment alongside some of the brightest minds in the industry on next generation, internet‑scale technology that directly impacts how customers use Machine Learning acceleration. Your expertise will be instrumental in validating the I/O technologies that enable our custom silicon to scale beyond what was previously possible.

Key Job Responsibilities

• Validate high‑speed interfaces (HBM, PCIe, UCIe, custom SerDes) end‑to‑end from PHY training through sustained traffic.
• Perform electrical characterization: eye diagrams, jitter analysis, voltage margin, and equalization tuning.
• Execute protocol‑level compliance testing and interoperability validation against industry specifications.
• Stress‑test links across PVT (Process, Voltage, Temperature) corners and aging conditions.
• Debug link training failures, bit errors, and performance degradation using lab instrumentation and silicon debug features.
• Collaborate with PHY design teams on equalization optimization, margin improvement, and silicon feedback.

Basic Qualifications

• 3+ years of non‑internship professional software development experience.
• 2+ years of non‑internship design or architecture experience of new and existing systems.
• Experience with RF measurement equipment (power meters, spectrum analyzers, vector signal generators, network analyzers, oscilloscopes).
• Bachelor's degree in Computer Science, Computer Engineering, or Electrical Engineering, or experience in test setup automation using MATLAB, Python, or Perl.
• 3+ years of hands‑on experience validating or characterizing at least one high‑speed interface technology (HBM, PCIe, DDR, SerDes, or UCIe).
• Proficiency with signal integrity measurement techniques: eye diagram analysis, jitter decomposition, and voltage/timing margin assessment.
• Familiarity with at least one interface specification standard (JEDEC HBM/DDR, PCI‑SIG PCIe, or UCIe consortium).

Preferred Qualifications

• 3+ years of full software development life cycle experience, including coding standards, code reviews, source control management, build processes, testing, and operations.
• Experience with HBM PHY training sequences and characterization.
• Knowledge of forward error correction (FEC) and link reliability metrics (BER, MTBF).
• PCB and package‑level signal integrity awareness (S‑parameters, channel modeling).
• Experience with multi‑die or chiplet architectures and die‑to‑die interconnect validation.
• Familiarity with equalization techniques (CTLE, DFE, FFE) and adaptive tuning.

Location and Compensation

Location: Austin, TX, USA

Salary: $143,700.00 – $194,400.00 USD annually.

Benefits include health insurance, 401(k) matching, paid time off, and parental leave. For more information about our benefits, visit https://amazon.jobs/en/benefits.

Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.