Sr. Signal Integrity / Power Integrity Engineer, Annapurna Labs, Machine Learning Hardware (AWS)

Amazon; Austin (TX); On-site; USD 159,200 - 215,300; Full time

Benefits offered by this job

Health, dental, vision insurance

401(k) matching

Paid time off

Job summary

Amazon's Annapurna Labs in AWS seeks a Senior SI/PI Engineer to define, design and validate next‑gen ML ASICs. You will lead end‑to‑end SI/PI activities, collaborate with hardware, validation and product teams, and influence stack‑ups and manufacturing feasibility.

In this on‑site role in Austin, TX, you will use ADS, MATLAB, Cadence and HFSS to model high‑speed channels, optimize PCIe interfaces, and minimize jitter and losses while ensuring reliable production.

Qualifications

• Deep understanding of SI concepts and strong analytical skills.
• Hands-on experience with ADS, MATLAB, Cadence, HFSS and others.
• Proficiency in high-speed channel simulations, including system-level modeling and validation.
• Experience with PCIe protocols and equalization methods (DFE, CTLE, FFE).
• Knowledge of clock distribution and jitter analysis for high-speed designs.
• Expertise in PCB layout and board manufacturing processes, including identifying and mitigating potential issues.
• Hands-on experience in stack-up design, including dielectric material selection, impedance control, and layer optimization.

Responsibilities

• Perform end-to-end high-speed channel simulations to ensure SI across designs.
• Conduct SI/PI analysis to optimize PCB layouts, minimizing losses and signal degradation.
• Utilize simulation tools such as ADS, MATLAB, Cadence, HFSS, and others to evaluate performance.
• Work with PCIe protocols and equalization techniques (DFE, CTLE, FFE) to optimize high‑speed interfaces.
• Analyze clock distribution and jitter, ensuring signal timing and integrity across designs.
• Collaborate with PCB layout and hardware design teams to define optimal stack‑ups and trade‑offs for manufacturing feasibility and performance.
• Identify and mitigate PCB manufacturing issues, ensuring high production yield and reliability.
• Work closely with cross‑functional teams, including hardware design, validation, and product engineering, to align on requirements and trade‑offs.

Skills

Signal Integrity

Power Integrity

PCIe protocols

Simulation tools

PCB layout

Clock distribution

Tools

ADS

MATLAB

Cadence

HFSS

Job description

Sr. Signal Integrity / Power Integrity Engineer, Annapurna Labs, Machine Learning Hardware

Annapurna Labs (our organization within AWS) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.

We are seeking a Senior SI/PI Engineer (Signal Integrity and Power Integrity) who will play a key role in the definition, design and validation of AWS next‑generation machine learning ASICs. As a senior member of our hardware team, you will have a meaningful opportunity to participate in the design and execution of all SI related topics, with the goal of creating and customized platforms that fit within AWS datacenter’s world leading technology.

Key Responsibilities

• Perform end‑to‑end high‑speed channel simulations to ensure signal integrity across complex designs.
• Conduct SI/PI analysis to optimize PCB layouts, minimizing losses and signal degradation.
• Utilize simulation tools such as ADS, MATLAB, Cadence, HFSS, and others to evaluate performance and troubleshoot issues.
• Work with PCIe protocols and equalization techniques (DFE, CTLE, FFE) to optimize high‑speed interfaces.
• Analyze clock distribution and jitter, ensuring signal timing and integrity across designs.
• Collaborate with PCB layout and hardware design teams to define optimal stack‑ups and trade‑offs for manufacturing feasibility and performance.
• Identify and mitigate PCB manufacturing issues, ensuring high production yield and reliability.
• Work closely with cross‑functional teams, including hardware design, validation, and product engineering, to align on requirements and trade‑offs.

Basic Qualifications

• Deep understanding of SI concepts and strong analytical skills in signal and power integrity.
• Hands‑on experience with simulation tools such as ADS, MATLAB, Cadence, HFSS, and others.
• Proficiency in high‑speed channel simulations, including system‑level modeling and validation.
• Experience with PCIe protocols and equalization methods (DFE, CTLE, FFE).
• Knowledge of clock distribution and jitter analysis for high‑speed designs.
• Expertise in PCB layout and board manufacturing processes, including identifying and mitigating potential issues.
• Hands‑on experience in stack‑up design, including dielectric material selection, impedance control, and layer optimization.

Preferred Qualifications

• Experience in power integrity analysis and power delivery network (PDN) optimization.
• Familiarity with high‑speed design compliance testing and validation methodologies.
• Knowledge of EMC/EMI mitigation techniques.

Compensation and Benefits

Base salary range: USD 159,200.00 – 215,300.00 annually (Austin, TX). Compensation includes sign‑on payments, restricted stock units and benefits such as health, dental, vision insurance, 401(k) matching, paid time off and parental leave. For more details see Amazon benefits page.

Equal Employment Opportunity

Amazon is an equal‑opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. If you have a disability and need a workplace accommodation or adjustment, please consult Amazon’s accommodations page.