Head of Ultra-Low Latency Trading Engine

Gate; United States; Remote; USD 180,000 - 300,000; Full time

Job summary

Gate is seeking a senior engineer to architect and implement the next-generation matching engine for a leading digital asset platform. You will design matching models, order book structures, memory management, and lock-free concurrency to support tens of millions of users.

You will set extreme latency and throughput standards, quantify core metrics, build resilient disaster recovery, multi-active setups, and lead a world-class team to push engineering excellence in a high-stakes crypto exchange

Qualifications

• Experience designing high-performance, low-latency systems for financial markets.
• Hands-on work with high-frequency trading platforms and exchange tech.
• Deep knowledge of CPU caches, network stacks, and kernel tuning.
• Ability to balance theoretical models with production constraints.
• Proven track record leading architecture decisions under volatility.

Responsibilities

• Lead architectural design and implementation of the next-gen matching engine.
• Define latency and throughput metrics such as TPS and P99/P999 latency.
• Build high-availability disaster recovery and multi-active fault tolerance.
• Foster a world-class engineering culture and drive capability upgrades.

Skills

High-performance systems

High-concurrency

HFT experience

Crypto exchange experience

Low-latency optimization

CPU cache optimization

System architecture

Latency analysis

Job description

Gate is seeking a senior engineer to architect and implement the next-generation matching engine for a leading digital asset platform. You will design matching models, order book structures, memory management, and lock-free concurrency to support tens of millions of users.

You will set extreme latency and throughput standards, quantify core metrics, build resilient disaster recovery, multi-active setups, and lead a world-class team to push engineering excellence in a high-stakes crypto exchange