HBM SoC RTL Design Intern: AI‑Driven Silicon

Micron Technology, Inc; Folsom (CA); On-site; USD 81,000 - 104,000; Full time

Job summary

Micron Technology, Inc. is seeking a SoC Design Engineer Intern to contribute to the design, development and integration of next‑generation HBM logic die in the Heterogeneous Integration Group.

You will work with architecture, verification, physical design, firmware, and product teams to deliver high‑performance RTL implementations. You will help validate and bring-up silicon, collaborate across multiple functions, and assist in design reviews while gaining exposure to industry-leading memory

Qualifications

• Pursuing a Bachelor's or Master's degree in electrical engineering, computer engineering, or related field.
• Cannot graduate prior to December 2027, and must be available for a 6-month internship.
• Proficiency in SystemVerilog/Verilog and familiarity with SoC integration methodologies.
• Experience with RTL-to-GDS flow, including synthesis, static timing analysis, and sign-off considerations.
• Familiarity with EDA tools from Cadence, Synopsys, and/or Siemens.
• Programming or scripting experience (Python, TCL, Perl, or shell).

Responsibilities

• Design and implement RTL for SoC-level blocks and subsystems used in HBM logic die.
• Integrate internal and third-party IP (controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY-adjacent logic).
• Collaborate with SoC architects to translate specifications into RTL implementations.
• Participate in SoC-level integration activities (clocking, reset, power, configuration).
• Assist with pre-silicon validation and post-silicon bring-up; root-cause analysis of silicon issues.
• Contribute to design documentation, block specifications, and design reviews.
• Collaborate with Product Engineering, Test, Process, and Manufacturing for robust builds.

Skills

SystemVerilog/Verilog

RTL-to-GDS flow

EDA tools (Cadence/Synopsys/Siemens)

Python/TCL/Perl/shell scripting

SoC integration methodologies

HBM/DRAM/memory-centric designs

Agentic AI awareness

Education

Bachelor’s or Master’s in Electrical/Computer Engineering

Eligibility: not graduating before Dec 2027

Job description

Micron Technology, Inc. is seeking a SoC Design Engineer Intern to contribute to the design, development and integration of next‑generation HBM logic die in the Heterogeneous Integration Group.

You will work with architecture, verification, physical design, firmware, and product teams to deliver high‑performance RTL implementations. You will help validate and bring-up silicon, collaborate across multiple functions, and assist in design reviews while gaining exposure to industry-leading memory