Hardware Tools Engineer

OpenAI; United States; Remote; USD 180,000 - 240,000; Full time

Job summary

OpenAI’s Hardware organization builds AI-native silicon and system-level solutions to power frontier models. This role develops and evolves the tooling ecosystem used by hardware engineers daily, spanning compilers, IR transformations, simulation, debugging, and automation infrastructure.

You will collaborate with architects, RTL designers, and verification engineers to translate real engineering friction into scalable tools, with hands-on work down to gate-level views when necessary.

Qualifications

• Experience building tooling ecosystems for hardware design.
• Strong knowledge of compilers, IRs, and RTL workflows.
• Experience with Verilog/SystemVerilog and hardware simulation.

Responsibilities

• Build and improve tooling for hardware teams, including compilers, IR passes, and code generation.
• Extend hardware compiler stacks and connect them to real design workflows.
• Improve developer experience with reproducible builds and CI.
• Collaborate with RTL designers and verification engineers to reduce friction.

Skills

Software engineering

Compiler concepts

Hardware workflows

RTL debugging

CI/CD

Education

Bachelor's degree in Computer Science or Electrical Engineering

Tools

Verilog/SystemVerilog

Verilator

VCS

Job description

About the Team

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform.

About the Role

About the Role You will develop and evolve the tooling ecosystem that hardware engineers rely on every day — from hardware compilers and IR transformations to simulation, debugging, and automation infrastructure. The work spans software engineering, compiler concepts, and practical hardware workflows, with direct impact on how quickly and effectively we design next-generation AI systems. You’ll collaborate closely with architects, RTL designers, and verification engineers to translate real engineering friction into durable, scalable tooling solutions. In this role you will: Build and improve the software tooling that makes hardware teams faster: compilation, IR transforms, RTL generation, simulation, debug, and automation. Extend and integrate hardware compiler stacks (frontends, IR passes, lowering, scheduling, codegen to Verilog/SystemVerilog) and connect them to real design workflows. Improve developer experience and reliability: reproducible builds, better error messages, faster iteration loops, and dependable CI and regression infrastructure. Work closely with designers and verification engineers to turn real pain points into durable tools. Dive into RTL when needed: read and reason about Verilog/SystemVerilog to debug issues, validate tool output, and improve debuggability. Be willing to go all the way down the stack when necessary, including gate-level views, synthesis results, and implementation artifacts. Help enable PPA optimization loops by building analysis and au