Hardware / Software CoDesign Engineer - 3P

OpenAI; United States; Hybrid; USD 150,000 - 190,000; Full time

Benefits offered by this job

Relocation assistance

Job summary

OpenAI is hiring an Engineer for the hardware optimization and co-design team in San Francisco, CA. You will collaborate with kernel, compiler, and ML engineers to tailor hardware for AI workloads, focusing on ML techniques, numerical approximations, and compiler optimizations.

The role involves working with vendors to shape future hardware architectures for efficient training and inference. The position offers a hybrid work model (3 days in the office) and relocation assistance for new

Responsibilities

• Co-design future hardware for programmability and performance with our hardware vendors
• Assist hardware vendors in developing optimal kernels and add support for it in our compiler
• Develop performance estimates for critical kernels for different hardware configurations and drive decisions on compute core and memory hierarchy

Job description

About the Team

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role

As an Engineer on our hardware optimization and co-design team, you will co-design future hardware from different vendors for programmability and performance. You will work with our kernel, compiler and machine learning engineers to understand their unique needs related to ML techniques, algorithms, numerical approximations, programming expressivity, and compiler optimizations. You will evangelize these constraints with various vendors to develop and influence future hardware architectures towards efficient training and inference on our models. If you are excited about efficiently distributing a large language model across devices, dealing with and optimizing system-wide/rack-wide networking bottlenecks and eventually tailoring the compute pipe and memory hierarchy of the hardware platform, simulating workloads at different abstractions and working closely with our partners, this is the perfect opportunity! This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.

Key Responsibilities

• Co-design future hardware for programmability and performance with our hardware vendors
• Assist hardware vendors in developing optimal kernels and add support for it in our compiler
• Develop performance estimates for critical kernels for different hardware configurations and drive decisions on compute core and memory h