Hardware Platform Security Architect - Trusted Compute

OpenAI; San Francisco (CA); On-site; USD 190,000 - 230,000; Full time

Job summary

OpenAI is seeking a Senior Hardware Platform Security Architect to own hardware security across silicon, firmware, and system layers within its trusted computing and cryptographic program.

You will co-architect secure silicon, secure hardware, and secure systems, deploying TPM2, Secure Boot, Nitro Enclaves, Intel SGX, and AMD-SEV at scale while collaborating across kernel, compiler, and infrastructure teams to align security with performance.

Qualifications

• 10+ years in hardware security or hardware-software co-design.
• Experience deploying secure hardware at scale.
• Strong coding in Rust and/or C/C++, Python.

Responsibilities

• Co-Architect Secure Silicon: Collaborate with cross-functional silicon teams to develop secure silicon that meets end-to-end system requirements.
• Co-Architect Secure Hardware: Collaborate with hardware vendors and cross-functional teams to design secure hardware meeting performance and security needs.
• Co-Architect Secure Systems: Architect and deploy systems using TPM2, Secure Boot, Nitro Enclaves, Intel SGX, AMD-SEV, and other secure technologies.
• Drive Innovation: Align hardware innovations with OpenAI's trusted computing and cryptographic requirements.

Skills

Hardware security

Hardware-software co-design

Rust

C/C++

Python

Cross-functional collaboration

Debug complex systems

Education

Advanced degree in Computer Architecture

Tools

TPM2 / Secure Enclave technologies

Intel SGX

AMD-SEV

Job description

OpenAI is seeking a Senior Hardware Platform Security Architect to own hardware security across silicon, firmware, and system layers within its trusted computing and cryptographic program.

You will co-architect secure silicon, secure hardware, and secure systems, deploying TPM2, Secure Boot, Nitro Enclaves, Intel SGX, and AMD-SEV at scale while collaborating across kernel, compiler, and infrastructure teams to align security with performance.