Lead Platform Security Architect for Silicon AI Compute

Neurophos; Austin (TX); On-site; USD 150,000 - 210,000; Full time

Benefits offered by this job

Health plan premiums covered

HSA contributions

Unlimited PTO

401(k) matching

Stock options

Job summary

Neurophos seeks a Principal Platform Security Architect to own platform security across EICs and the T100 system. This product-security role partners with RTL designers and firmware engineers to verify silicon through secure boot, device attestation, OTA updates, and telemetry.

You will lead RoT integration and drive security in hyperscaler discussions, reporting to the VP of Architecture. The role requires 10+ years in hardware/firmware security on silicon, strong communication skills, and a

Qualifications

• BS/MS/PhD in CS, EE or related field and 10+ years hardware/firmware security on silicon.
• Experience integrating root-of-trust IP including provisioning and OTP planning.
• Secure boot chain design and firmware resiliency per NIST SP 800-193 class requirements.
• Familiarity with SPDM, DICE, MCTP and PLDM; cryptography basics in silicon.
• Ability to write security specs for design/firmware teams and defend decisions.

Responsibilities

• Own platform threat model and security architecture from fab to field.
• Architect RoT integration, provisioning, fuse/OTP strategy, and debug authorization.
• Define secure/measured boot chain and firmware resiliency behavior.
• Own device attestation using SPDM with DICE identity.
• Define OTA firmware update with anti-rollback protection.
• Specify security telemetry for datacenter operators.
• Drive compliance with OCP and DMTF specs.
• Own key management lifecycle across manufacturing and field processes.
• Serve as technical owner for outsourced RoT subsystem engagement.
• Support hyperscaler security reviews and articulate security narrative.
• Partner with design, firmware, and systems teams to land security requirements.

Skills

Platform security

Root of trust

Secure boot

Firmware security

Threat modeling

RTL liaison

Communication skills

Education

BS/MS/PhD in CS/EE

Tools

SPDM

DICE

MCTP

PLDM

Job description

Neurophos seeks a Principal Platform Security Architect to own platform security across EICs and the T100 system. This product-security role partners with RTL designers and firmware engineers to verify silicon through secure boot, device attestation, OTA updates, and telemetry.

You will lead RoT integration and drive security in hyperscaler discussions, reporting to the VP of Architecture. The role requires 10+ years in hardware/firmware security on silicon, strong communication skills, and a