Hardware Engineering, Architect-17965

Synopsys Inc; United States; On-site; USD 120,000 - 180,000; Full time

Job summary

Synopsys Inc. is seeking an expert to perform interconnect assessments, optimize power integrity, and document design guidelines for high‑speed PHY components in cutting‑edge silicon and software products.

You will work with design teams and customers to refine signal and power analysis methods, contribute to DDR/HBM PHY roadmaps, and help advance SIPI methodologies across projects.

Qualifications

• Deep understanding of high‑speed interface signaling operations (s-parameters, jitter, eye diagrams).
• Experience communicating results and recommendations within design teams and to customers.
• Knowledge of board-level construction and on‑chip IO design operation.

Responsibilities

• Perform interconnect assessments to predict channel data rates and signal margins.
• Assess power delivery systems to optimize power integrity and jitter minimization.
• Document findings in reports and design guidelines; drive recommendations to customers and teams.
• Interact with design teams and customers to apply signal and power analysis methods to problems.
• Keep up with DDR/HBM PHY roadmap developments and contribute to strategy.

Skills

High-speed interface signaling

Board-level IO design

Independent issue closure

Communicate results to teams

Tools

HFSS

Ansys

HSPICE

Raptor

ADS

Job description

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self‑driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high‑performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

What You’ll Be Doing

• Perform interconnect assessments using the latest modeling techniques to predict channel data rates and signal margins.
• Assess strategies for system performance optimization, including signal margins, power, and FFE, DFE, and CTLE equalization techniques.
• Assess power delivery systems to optimize power integrity for supply stability and jitter minimization.
• Document findings in reports and design guidelines.
• Communicate results and insights to design teams to improve PHY design.
• Communicate results and recommendations to customers to enable them to optimize their system performance.
• Interact with design teams and customers to refine and apply signal and power analysis methods to address problems.
• Understand Synopsys’ DDR and HBM PHY roadmap and create strategies for improved performance.
• Track industry developments through activities at standards committees and memory vendor roadmaps.

What You’ll Need

• Proven understanding of high‑speed interface signaling operation, such as s‑parameters, channel loss, crosstalk, equalization techniques, jitter, and power delivery modeling.
• Well‑versed in signal and power delivery analysis methods, including eye diagram construction through statistical modeling, return loss, impedance matching, and resonant system analysis.
• Ability to use HFSS and Ansys tools, HSPICE, Raptor, and ADS.
• Skilled in generating and communicating results, findings, conclusions, and recommendations within a design team and to external customers.
• Knowledgeable in board‑level construction and on‑chip IO design operation.

The Impact You Will Have

• Enhance the performance and reliability of high‑speed interface designs.
• Drive improvements in system performance optimization techniques, contributing to lower power consumption and higher data rates.
• Optimize power delivery systems, ensuring supply stability and minimized jitter.
• Provide critical insights and recommendations that will shape the design and development of PHY components.
• Enable customers to achieve optimal system performance through expert guidance.
• Contribute to the advancement of SIPI methodologies and their adoption by customers.
• Help refine strategies to address signal and power integrity challenges in cutting‑edge technologies.
• Influence the direction of Synopsys’ DDR and HBM PHY roadmap.
• Maintain a leadership position in technological innovation.

Who You Are

• A team player able to communicate clearly and efficiently.
• Ability to independently lead issues to full closure.

The Team You’ll Be A Part Of

The R&D circuits team is tasked with providing SIPI solutions for the future DDR/HBM topologies and protocols, identifying key enablers, and supporting early adopters or critical customers. We also develop SIPI methodologies to be adopted by customers and manage interconnect budgeting.