GPU Kernel Engineer — Kernel Optimization & Compiler Innovation

SF Tensor; San Francisco (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

SF Tensor is building the fastest GPU compiler and a versatile kernel optimizer. We seek a Member of Technical Staff for GPU Kernel Engineering to push the envelope on what hardware can do before any search runs.

You will write and hand-optimize kernels that execute during pre-training, post-training and inference across NVIDIA, AMD, TPU and Trainium. You will convert kernel learnings into compiler-search structures, with access to an end-to-end stack down to the ISA.

Qualifications

• Track record of hand-writing kernels that beat vendor libraries or are on par with them.
• Strong C++/CUDA or ROCm/HIP low-level programming skills.
• Experience reading GPU ISA and machine-level assembly (PTX/SASS/GCN).
• Familiarity with profiling tools to diagnose microarchitectural bottlenecks.

Responsibilities

• Write and hand-optimize kernels for real workloads to maximize ceiling before search space exploration.
• Profile at microarchitectural level: SM/CU utilization, warp stalls, memory conflicts, register pressure.
• Debug down to clock behavior, thermal throttling and driver paths; ensure correctness with formal proof where applicable.
• Convert hard-won kernel knowledge into structures the compiler can search.
• Work below PTX at the ISA level, reasoning about SASS and cubins for schedules.
• Build performance models, microbenchmarks and tooling to predict kernel behavior.
• Collaborate with the formal correctness team to ship kernels with a formal proof when required.

Skills

Hand-tuned kernels

Low-level GPU programming

C++

CUDA

ISA familiarity

Performance profiling

Tools

Nsight Compute

Nsight Systems

rocprof

omniperf

Job description

SF Tensor is building the fastest GPU compiler and a versatile kernel optimizer. We seek a Member of Technical Staff for GPU Kernel Engineering to push the envelope on what hardware can do before any search runs.

You will write and hand-optimize kernels that execute during pre-training, post-training and inference across NVIDIA, AMD, TPU and Trainium. You will convert kernel learnings into compiler-search structures, with access to an end-to-end stack down to the ISA.