GPU Graphics Cache Verification Engineer

Apple Inc.; Santa Clara (CA); On-site; USD 150,400 - 277,600; Full time

Benefits offered by this job

Employee stock programs

Medical and dental coverage

Education reimbursement

Relocation assistance

Job summary

Apple Inc. in Santa Clara, CA seeks a Graphics Cache Hierarchy Verification Engineer to drive pre-silicon RTL verification of graphics memory subsystems and related units.

You will design verification plans, build reusable test benches, and generate directed and constrained tests to ensure robust performance. The role requires a strong background in CPU/GPU architecture, SystemVerilog verification, HDL simulators, and UVM-style methodologies, collaborating across blocks to achieve comprehensive

Qualifications

• BS degree with 3+ years of hardware verification experience.
• Experience with CPU or GPU architecture.
• Experience with verification languages such as SystemVerilog.

Responsibilities

• Develop verification plans with design leads and architects.
• Build and maintain portable verification test bench components and environments.
• Generate directed and constrained random tests.
• Run simulations and debug design and environment issues.
• Create functional coverage points, analyze coverage and improve test environment to cover holes.
• Create automated verification flows for block verification.
• Apply knowledge of VHDL/Verilog to verify complex designs.
• Collaborate with memory subsystem and core engineers for seamless verification flow.

Skills

CPU/GPU architecture

SystemVerilog

HDL simulators

UVM

Perl/Ruby/Shell scripting

Education

BS degree

Job description

Apple Inc. in Santa Clara, CA seeks a Graphics Cache Hierarchy Verification Engineer to drive pre-silicon RTL verification of graphics memory subsystems and related units.

You will design verification plans, build reusable test benches, and generate directed and constrained tests to ensure robust performance. The role requires a strong background in CPU/GPU architecture, SystemVerilog verification, HDL simulators, and UVM-style methodologies, collaborating across blocks to achieve comprehensive