GPU Driver & Memory Management Architect

HP; Spring (TX); On-site; USD 147,000 - 231,000; Full time

Benefits offered by this job

Health insurance

Dental insurance

Vision insurance

Disability insurance

Employee assistance program

Flexible spending account

Life insurance

Generous paid leave

Paid holidays

Flexible paid vacation and sick leave

Job summary

HP in United States seeks a highly experienced GPU Driver & Memory Management Architect to own driver-level memory management across CPU, GPU, and NPU. The role focuses on scalable architectures, identifying new technologies, and driving performance improvements for AI workloads.

Ideal candidates have 10+ years in electrical design, with strong memory/GPU expertise, and experience collaborating with IHVs. The position is full-time with competitive benefits.

Qualifications

• Four-year or Graduate Degree in Electrical Engineering or related discipline.
• Typical has 10+ years of work experience in electrical design and related fields.
• Strong knowledge of memory/GPU design and hardware architectures.

Responsibilities

• Architect driver-level memory management (DVMT, shared memory models, WDDM).
• Enable dynamic memory allocation across GPU, CPU, and NPU.
• Optimize iGPU performance for AI + graphics hybrid workloads.
• Define OS-driver contracts (Windows/Linux).
• Diagnose memory-related performance bottlenecks.
• Partner with IHVs on driver capabilities and requirements.

Skills

Memory/GPU design

Electrical Engineering

Computer Science

Debugging

Hardware Architecture

Hardware Design

FPGA

MATLAB

Oscilloscope

Schematic Capture

Systems Design

Education

Electrical Engineering degree (Four-year or Graduate)

Tools

MATLAB

Oscilloscope

Schematic Capture

Job description

GPU Driver & Memory Management Architect

Description -

Job Summary

This role is responsible for exploring & developing GPU (and NPU-adjacent) driver architecture with deep ownership of memory management, enabling efficient shared memory utilization across CPU/GPU/NPU. This role ensures architectures and methodologies are scalable across different PCs, identifying and evaluating emerging technologies and partnerships, and aligning these with technology roadmaps and business value. The role will deliver improved GPU/NPU utilization for AI workloads. The role offers tangible feedback to enhance product quality, while overseeing tracking and reporting of product-related performance metrics. The role leverages functional expertise to shape strategy and policy, facilitating the realization of operational and strategic plans.

Responsibilities

• Architect driver-level memory management (DVMT, shared memory models, WDDM)
• Enable dynamic memory allocation across GPU, CPU, and NPU
• Optimize iGPU performance for AI + graphics hybrid workloads
• Define OS-driver contracts (Windows/Linux)
• Diagnose and resolve memory-related performance bottlenecks
• Partner with IHVs (Intel/AMD/Qualcomm) on driver capabilities and requirements

• Develops organization-wide architectures and methodologies for electrical hardware design and development across multiple platforms and organizations.
• Leads part qualification processes through implementation of product quality plans, equipment inspections, factory witness testing, and manufacturing process qualifications.
• Identifies and evaluates new technologies, innovations, and outsourced development partner relationships for alignment with technology roadmap and business value.
• Drives integration of new technologies into projects and activities in the electrical hardware design organization.
• Reviews and evaluates designs and project activities for compliance with technology and development guidelines and standards; provides tangible feedback to improve product quality.
• Leads overall tracking and reporting of various electrical/hardware product related performance metrics and reports against the same.
• Exercises independent judgment in resolving business issues and establishing functional policies for guidance.
• Provides domain-specific expertise and overall electrical/electronic hardware and platform leadership and perspective to cross-organization projects, programs, and activities.
• Leverages functional expertise in guiding strategy and setting functional policy and direction, while helping the team in realization of these operational and strategic plans.
• Provides guidance and mentoring to less- experienced staff members to set an example of electrical hardware design and development, innovation, and excellence.

Education & Experience Recommended

Four-year or Graduate Degree in Electrical Engineering, or any other related discipline or commensurate work experience or demonstrated competence.

Typical has 10+ years of work experience, preferably in electrical design and tools, software packages, architecture of electronic hardware, or a related field.

Preferred Certifications

NA

Knowledge & Skills

• Memory/GPU design
• Computer Engineering
• Computer Science
• Debugging
• Electrical Engineering
• Electronic Engineering
• Electronics
• Field-Programmable Gate Array (FPGA)
• Hardware Architecture
• Hardware Design
• MATLAB
• Mechanical Engineering
• New Product Development
• Oscilloscope
• Physics
• Printed Circuit Board
• Schematic Capture
• Simulations
• Systems Design

Cross-Org Skills

• Effective Communication
• Results Orientation
• Learning Agility
• Digital Fluency
• Customer Centricity

Impact & Scope

• Impacts large functions and leads large, cross-division functional teams or projects.

Complexity

• Provides highly innovative solutions to complex problems within established policy.

Disclaimer

This job description describes the general nature and level of work performed in this role. It is not intended to be an exhaustive list of all duties, skills, responsibilities, knowledge, etc. These may be subject to change and additional functions may be assigned as needed by management.

The pay range for this role is $147,050 to $230,850 USD annually with additional opportunities for pay in the form of bonus and/or equity (applies to United States of America candidates only). Pay varies by work location, job-related knowledge, skills, and experience.

Benefits:

HP offers a comprehensive benefits package for this position, including:

• * Health insurance
• * Dental insurance
• * Vision insurance
• * Long term/short term disability insurance
• * Employee assistance program
• * Flexible spending account
• * Life insurance
• * Generous time off policies, including;
• * 4-12 weeks fully paid parental leave based on tenure
• * 11 paid holidays
• * Additional flexible paid vacation and sick leave (US benefits overview [https://hpbenefits.ce.alight.com/])

The compensation and benefits information is accurate as of the date of this posting. The Company reserves the right to modify this information at any time, with or without notice, subject to applicable law.

Job -

Engineering

Schedule -

Full time

Shift -

No shift premium (United States of America)

Travel -

Relocation -

Equal Opportunity Employer (EEO) -

HP, Inc. provides equal employment opportunity to all employees and prospective employees, without regard to race, color, religion, sex, national origin, ancestry, citizenship, sexual orientation, age, disability, or status as a protected veteran, marital status, familial status, physical or mental disability, medical condition, pregnancy, genetic predisposition or carrier status, uniformed service status, political affiliation or any other characteristic protected by applicable national, federal, state, and local law(s).

Please be assured that you will not be subject to any adverse treatment if you choose to disclose the information requested. This information is provided voluntarily. The information obtained will be kept in strict confidence.

For more information, review HP's EEO Policy or read about your rights as an applicant under the law here: "Know Your Rights: Workplace Discrimination is Illegal"