GPU Design Verification Engineer

Canvendor; San Jose (CA); On-site; USD 133,000 - 187,000; Full time

Job summary

A leading company in semiconductor manufacturing is seeking a Design Verification Engineer for a contract role in San Jose, CA. The ideal candidate will have extensive experience in design verification, proficiency in System Verilog and UVM, and a strong understanding of micro-architecture. This role involves collaborating with architects to build verification environments, developing test strategies, and analyzing test results. If you are passionate about GPU design and want to work in a dynamic environment, apply now!

Qualifications

• 5+ years of industry experience in a design verification role.
• Experience with code coverage and functional coverage-driven verification.

Responsibilities

• Build verification environments and test plans with architects and designers.
• Develop assertions and checks to optimize isolation time.
• Analyze failing tests and provide input on specifications.

Skills

System Verilog

UVM

OOP

C++

Python

Perl

Education

BS in Computer Engineering

MS CE/EE

Job description

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IT & Engineering Recruiter at Canvendor | Hiring for Fulltime/Contract Consultants. Drop your Resume E: [e-mail]

We do have a GPU Design Verification Engineer role in San Jose, CA or Austin, TX (Onsite). Please find the Job Description below and kindly respond back with your updated resume.

Job Location: San Jose, CA or Austin, TX (Onsite)

Duration: 12+ Months

Job Description:

• Work with architects and designers to build verification environments and test plans
• Craft functional verification coverage strategy to ensure complete test suite implementation
• Develop assertions and checks to optimize isolation time and produce meaningful failing signatures
• Analyze failing tests to root cause along, working with RTL and reference modeling teams
• Provide input on Architectural and Micro-Architectural specifications for testability and accuracy
• Examine code coverage results, identifying exclusions and improving stimulus
• Take ownership of key milestone closure by meeting phase gate pass rates, coverage quality, and other quality metrics

Skills and Qualifications:

• BS in Computer Engineering, BSEE or comparable and 5+ years of industry experience in a design verification role
• Proficient in System Verilog/UVM/OVM, and OOP/C++
• Deep understanding of constrained randomization and the development of efficient test suites
• Experience with code coverage and functional coverage-driven verification methodology. • Experience in creating, running and debugging of System Verilog/UVM constraint-random testbench.
• Working knowledge of scripting languages such as Python or Perl
• Understanding of micro-architecture, logic design, FSMs, arithmetic Datapath pipelines

Preferred qualifications:

• MS CE/EE with 5+ years of industry experience in verification
• Good verbal and written communication skills
• Experience of GPU or CPU is a plus

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Contract

Job function

• Industries

  Semiconductor Manufacturing

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