GNSS Design Verification Engineer

Apple Inc.; San Diego (CA); On-site; USD 115,000 - 175,000; Full time

Job summary

Join a world-class modem team at a leading company, where you'll craft sophisticated embedded firmware and innovate new cellular technologies. This role demands collaboration across product development and strong technical skills in verification and digital logic design, offering competitive compensation and benefits.

Benefits

Stock programs

Medical and dental coverage

Retirement plans

Educational reimbursement

Relocation assistance

Qualifications

• Bachelor’s degree or higher required; MSEE preferred.
• Strong knowledge of digital design and verification methodologies.
• Experience in scripting and debugging required.

Responsibilities

• Build block/subsystem/chip level testbench using advanced DV methodologies.
• Develop verification plans and manage bug tracking.
• Perform low power verification and improve DV methodologies.

Skills

Digital logic design principles

Scripting languages (Shell, Python, Perl)

Verification techniques

Problem-solving

Constrained random testing

Debugging

Education

Bachelor’s degree or higher

MSEE or higher preferred

Tools

SystemVerilog

UVM

SystemVerilog Assertion (SVA)

Job description

Do you have a passion for invention and self-challenge? Do you thrive on pushing the limits of what’s considered feasible? As part of a world-class modem team, you’ll craft sophisticated groundbreaking embedded firmware that delivers more performance in our products than ever before. You’ll work across fields to transform improved hardware elements into a single, integrated design. Join us, and you’ll help us innovate new cellular technologies that continually outperform previous iterations! By collaborating with other product development groups across Apple, you’ll push the industry boundaries of what wireless systems can do and improve the product experience for our customers worldwide.

Description

• Build block/subsystem/chip level testbench using advanced DV methodologies.
• Develop verification plans from specifications and review with designers and systems engineers.
• Architect testbenches with maximum reusability and build UVM libraries.
• Create directed and constrained-random tests, debug failures, manage bug tracking, and close coverage.
• Create and analyze block/subsystem level coverage models and add test cases to increase coverage.
• Perform low power verification and formal verification; improve DV flow and methodologies.

Minimum Qualifications

• Bachelor’s degree or higher.
• Strong understanding of digital logic design principles.
• Knowledge of scripting languages (Shell, Python, Perl).
• Experience with verification techniques including problem-solving, constrained random testing, and debugging.

Preferred Qualifications

• MSEE or higher preferred.
• Knowledge of SoC subsystem and low power verification experience.
• Experience with SystemVerilog Assertion (SVA).
• Experience in mixed-signal modeling and simulation.
• Knowledge of digital signal processing is preferred.
• Proficiency in SystemVerilog with a deep understanding of UVM.

At Apple, base pay is part of our total compensation package and is determined within a range. The range for this role is $115,700 to $174,200, depending on skills, qualifications, experience, and location.

Apple employees have opportunities for stock programs, benefits including medical and dental coverage, retirement plans, discounts, educational reimbursement, bonuses, and relocation assistance. Learn more about Apple Benefits.

Note: Benefits, compensation, and stock programs are subject to eligibility and other terms.

Apple is an equal opportunity employer committed to inclusion and diversity. We promote equal opportunity regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or other protected characteristics. Learn more about your EEO rights as an applicant.