FPGA IP Planner: PCIe/CXL & DMA Strategy

Altera; San Jose (CA); On-site; USD 149,000 - 216,000; Full time

Job summary

Altera, a leading FPGA IP provider, is seeking a seasoned Planner/Product Manager to drive the definition and prioritization of next-generation PCIe and CXL IP, including DMA. You will synthesize requirements from product roadmaps, market data, and engineering teams to shape timelines and deliverables.

You will partner with architecture and execution teams to ensure clear specs and aligned schedules, influencing cross-functional stakeholders and guiding IP strategy in a fast-paced, high-tech

Qualifications

• Bachelor's degree or equivalent in Electrical Engineering, CS, Computer Engineering, or related field.
• 10+ years in FPGA applications, IP, or related server/storage/accelerator domains with PCIe, CXL, DMA experience.
• Strong communication and collaboration skills.

Responsibilities

• Drive the definition, trade-off analysis, and convergence of next-generation hard and soft IP solutions for FPGA end markets and applications.
• Coordinate with business stakeholders and customers to translate requirements into the product roadmap.
• Generate specific product requirements and maintain a detailed IP product roadmap.
• Coordinate with peers to align interdependent programs and solutions.
• Manage input to engineering execution and change management processes.

Skills

Business acumen

Leadership

Presence & communications

Interpersonal skills

Initiative

Analytical skills

Education

Bachelor's degree in Electrical Engineering, Computer Science, Computer Engineering, or related field

Tools

PCIe

CXL

DMA

FPGA IP

Job description

Altera, a leading FPGA IP provider, is seeking a seasoned Planner/Product Manager to drive the definition and prioritization of next-generation PCIe and CXL IP, including DMA. You will synthesize requirements from product roadmaps, market data, and engineering teams to shape timelines and deliverables.

You will partner with architecture and execution teams to ensure clear specs and aligned schedules, influencing cross-functional stakeholders and guiding IP strategy in a fast-paced, high-tech