FPGA Host & Network IO Engineer | Ultra-Fast AI Clusters

Cerebras Systems; Sunnyvale (CA); On-site; USD 150,000 - 230,000; Full time

Job summary

Cerebras Systems is seeking an experienced FPGA engineer to own the Host and Network IO subsystems across Cerebras’ WSE platform. You will optimize bandwidth and latency, implement RDMA-based interfaces, and drive next-gen IO architectures for large AI clusters.

Responsibilities include RTL improvements, production bitstreams, and cross-team collaboration with DV, hardware, and software groups to deliver high-performance networking solutions.

Qualifications

• 5+ years producing FPGA solutions in industry or Master’s/PhD with 3+ years experience
• Proficient Verilog development in Git-based repos
• Strong placement & routing, timing closure, simulation, debug
• Familiar with TCP/RoCE networks and network debug tools
• Knowledge of network switch environments (Arista/Juniper)
• Experience with AI-augmented development environments

Responsibilities

• Lead full chassis-to-wafer IO architecture and design
• Improve RTL, implement next-gen FPGA design, define future IO architectures
• Produce production-ready bitstreams for large clusters
• Collaborate with DV team to prevent bugs and simplify debugging
• Optimize bandwidth/latency over FPGA datapath and IO interfaces
• Interface with board team for bringup
• Drive network performance debug for large AI clusters
• Integrate leading-edge networking technologies and protocols
• Lead cross-functional projects spanning software and hardware
• Foster clear communication across teams and stakeholders

Skills

Production FPGA

Verilog

FPGA tooling

Network protocol (TCP/RoCE)

Network debugging (Wireshark)

AI-augmented development

Education

Master’s/PhD in Computer or Electrical Engineering

Tools

Wireshark

Job description

Cerebras Systems is seeking an experienced FPGA engineer to own the Host and Network IO subsystems across Cerebras’ WSE platform. You will optimize bandwidth and latency, implement RDMA-based interfaces, and drive next-gen IO architectures for large AI clusters.

Responsibilities include RTL improvements, production bitstreams, and cross-team collaboration with DV, hardware, and software groups to deliver high-performance networking solutions.