Senior FPGA Network IO Architect for Ultra‑Fast AI Clusters

Cerebras; United States; Remote; USD 180,000 - 240,000; Full time

Job summary

The Host and Network IO Team develops the full IO path from server nodes to the Cerebras WSE, including RoCE v2 interfaces, a large programmable switching fabric, and serial IO with a proprietary protocol.

As an FPGA developer on the team, you will optimize bandwidth and latency, interface with AI application IO, cluster, and embedded software teams, and contribute to multi-generational hardware designs.

Qualifications

• 5+ years FPGA production experience or advanced degree with 3+ years industry experience.
• Proficiency in Verilog development in Git-based workflows.
• FPGA placement, routing, timing closure, and debug proficiency.
• Familiarity with network protocols (TCP, RoCE) and network debugging tools.
• Experience with network switch environments or willingness to learn.

Responsibilities

• Lead full chassis-to-wafer IO architecture and design.
• Improve RTL, implement next-gen FPGA design, define future IO architectures.
• Produce production-ready bitstreams for deployment into large clusters.
• Work with DV team to prevent bug slips and simplify debug.
• Optimize bandwidth/latency over FPGA datapath and all IO interfaces.
• Interface with board team facilitating and executing board bringup.
• Drive network performance debug of large AI clusters.
• Integrate leading edge networking technologies and protocols.
• Lead cross-functional technical projects spanning multiple teams and integrating diverse software and hardware components to deliver an improved network IO solution.
• Foster clear and effective communication across teams and stakeholders.

Skills

FPGA development

Verilog

Placement routing & timing closure

Network protocols (TCP, RoCE)

Debug tools (Wireshark)

Education

Master's/PhD in Computer or Electrical Engineering

Tools

Wireshark

Git-based Verilog workflows

Job description

The Host and Network IO Team develops the full IO path from server nodes to the Cerebras WSE, including RoCE v2 interfaces, a large programmable switching fabric, and serial IO with a proprietary protocol.

As an FPGA developer on the team, you will optimize bandwidth and latency, interface with AI application IO, cluster, and embedded software teams, and contribute to multi-generational hardware designs.