FPGA Hardware Engineering Intern — 10 Weeks, NYC

Two Sigma; New York (NY); On-site; USD 173,000 - 191,000; Full time

Benefits offered by this job

Onsite gym

Hybrid work policy

Job summary

Two Sigma is seeking software engineering interns for a 10-week summer program at our Soho, New York City office. You will design, test, and simulate digital logic for FPGA-based systems, work with RTL components, and collaborate across hardware, software, networking, and quantitative teams. You should be pursuing a Bachelor's, Master's, or PhD in EE/CE/CS.

Coursework in digital logic and Verilog/SystemVerilog is ideal. Basic Python/C/C++ skills required.

Qualifications

• Pursuing a bachelor’s, master’s, or PhD in EE/CE/CS or a related field.
• Completed coursework in digital logic, computer architecture, embedded systems, or related area.
• Familiarity with SystemVerilog/Verilog/VHDL.
• Basic programming in Python/C/C++ or similar language.
• Understanding of digital-design concepts: combinational/sequential logic, FSM, pipelining, clocked circuits.

Responsibilities

• Design, simulate, and test digital logic for FPGA-based systems with guidance from experienced engineers.
• Contribute to reusable RTL components and verification environments.
• Write tests and debugging tools using SystemVerilog, Python, or similar languages.
• Use simulation and waveform-analysis tools to investigate issues.
• Gain hands-on experience with synthesis, timing analysis, and FPGA workflows.
• Explore hardware-software interfaces and integrate components into larger systems.
• Collaborate with hardware, software, networking, and quantitative teams.
• Document work and present findings to the team.

Skills

SystemVerilog

Python

C++

Verilog

Digital logic

Education

Bachelor's/Master's in EE/CE/CS or related

Tools

FPGA toolchain

Job description

Two Sigma is seeking software engineering interns for a 10-week summer program at our Soho, New York City office. You will design, test, and simulate digital logic for FPGA-based systems, work with RTL components, and collaborate across hardware, software, networking, and quantitative teams. You should be pursuing a Bachelor's, Master's, or PhD in EE/CE/CS.

Coursework in digital logic and Verilog/SystemVerilog is ideal. Basic Python/C/C++ skills required.