FPGA Hardware Engineer Intern – High-Performance, Low-Latency

Akuna Capital; Chicago (IL); On-site; USD 130,500 - 159,500; Full time

Job summary

Akuna Capital is offering a 10-week Hardware Engineer Intern program on the FPGA Team in Chicago. Interns work with experienced Hardware and C++ Software Engineers to design and implement elegant solutions to complex problems, taking full ownership of their projects and presenting outcomes at program end.

You will work on high-performance, low-latency systems and contribute to automated trading algorithms with cutting-edge tech, while gaining training and education support throughout the

Qualifications

• Pursuing bachelor’s, master’s, or Ph.D. in Computer and Electrical Engineering, Computer Science, or a related field.
• Graduating by August 2029.
• GPA of 3.5 or above.
• Legal authorization to work in the U.S. on first day of employment (including F-1 CPT/OPT/STEM).

Responsibilities

• Own your project from inception to presentation after 10 weeks.
• Design and implement high-performance, low-latency FPGA solutions.

Skills

Verilog

SystemVerilog

VHDL

Analytical skills

Fast decision making

High-performance computing

Education

Bachelor's/Master's/PhD in EE/CS

Job description

Akuna Capital is offering a 10-week Hardware Engineer Intern program on the FPGA Team in Chicago. Interns work with experienced Hardware and C++ Software Engineers to design and implement elegant solutions to complex problems, taking full ownership of their projects and presenting outcomes at program end.

You will work on high-performance, low-latency systems and contribute to automated trading algorithms with cutting-edge tech, while gaining training and education support throughout the