Architecture Workload Datacenter & Agentic AI Workload Performance Optimization Engineer Santa Clara, California, United States; Toronto, Ontario, Canada

Tenstorrent; Santa Clara (CA); On-site; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent is seeking a Datacenter & Agentic AI Workload Performance Optimization Engineer to optimize workloads on next‑gen RISC‑V platforms. You will identify bottlenecks and craft software, compiler, and hardware‑aware optimizations across runtimes and AI workloads.

The role sits remotely in North America and welcomes varied experience levels; offers are aligned to level during interviews. You’ll work with a forward‑looking team on performance and scalability challenges facing datacenter AI

Qualifications

• Master’s or PhD in Computer Engineering, Electrical Engineering, Computer Science, or related field with strong experience in performance optimization, computer architecture, compilers, or systems software.
• Hands‑on experience with runtime or compiler optimization, such as OpenJDK/JIT, LLVM, GCC, V8, Python, or equivalent systems.
• Strong understanding of CPU performance, memory hierarchies, concurrency, garbage collection, vector/SIMD optimization, and RISC‑V architecture.
• Expertise with performance profiling and analysis tools such as Linux perf, runtime profilers, QEMU, tracing tools, and performance modeling environments.
• Strong programming skills in Java, Python, C/C++, and RISC‑V assembly, with the ability to work effectively across multiple software layers.

Responsibilities

• Optimize software workloads on next‑gen RISC‑V platforms and datacenter environments.
• Identify performance bottlenecks and implement software, compiler, runtime, and hardware‑aware optimizations.
• Profile real‑world applications and explore vector/SIMD and custom ISA optimizations.
• Collaborate across compiler, runtime, systems software, hardware, and performance modeling teams.
• Support AI‑assisted development and automated optimization workflows to accelerate performance engineering.

Skills

Performance optimization

RISC-V experience

Profiling

Cross-functional collab

CPU microarchitecture

Education

Master’s/PhD in Computer Engineering, Electrical Engineering, or Computer Science

Tools

Linux perf

QEMU

Tracing tools

Performance modeling

LLVM

Job description

Datacenter & Agentic AI Workload Performance Optimization Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Tenstorrent is looking for a Workload Performance Optimization Engineer to help optimize the software workloads that run on our next-generation RISC-V platforms. You’ll work across modern datacenter and agentic AI workloads—including Java, Python, PHP, Node.js, Lua, Go, and Rust—to identify performance bottlenecks and develop software, compiler, runtime, and hardware‑aware optimizations that improve throughput, latency, and efficiency. This role sits at the intersection of software runtimes, compilers, CPU microarchitecture, and RISC‑V silicon. You’ll bring up and tune major runtimes, profile real‑world applications, investigate memory and concurrency behavior, and explore optimizations using RISC‑V Vector/Matrix capabilities and custom instructions. You’ll also work with AI‑assisted development and automated optimization workflows to accelerate the performance engineering process. Your work will directly influence both the RISC‑V software ecosystem and the architecture of future Tenstorrent CPUs.

This role isremote, based out of North America.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You’re a performance engineer who enjoys getting deep into runtimes, compilers, applications, and CPU microarchitecture to understand why software is fast—or slow.
• You have hands‑on experience optimizing software on RISC‑V or another modern CPU architecture, with a strong understanding of the hardware/software boundary.
• You’re comfortable profiling complex systems, finding bottlenecks, forming hypotheses, and iterating through optimizations using data.
• You’re excited about emerging agentic AI development workflows and using AI tools to automate profiling, coding, benchmarking, and optimization.
• You’re a strong technical collaborator who can work across compiler, runtime, systems software, hardware, and performance modeling teams.

What We Need

• Master’s or PhD in Computer Engineering, Electrical Engineering, Computer Science, or a related field, with strong experience in performance optimization, computer architecture, compilers, or systems software.
• Hands‑on experience with runtime or compiler optimization, such as OpenJDK/JIT, LLVM, GCC, V8, Python, or equivalent systems.
• Strong understanding of CPU performance, memory hierarchies, concurrency, garbage collection, vector/SIMD optimization, and RISC‑V architecture.
• Expertise with performance profiling and analysis tools such as Linux perf, runtime profilers, QEMU, tracing tools, and performance modeling environments.
• Strong programming skills in Java, Python, C/C++, and RISC‑V assembly, with the ability to work effectively across multiple software layers.

What You Will Learn

• How to optimize modern software stacks from application and runtime all the way down to CPU microarchitecture and silicon.
• How RISC‑V Vector, Matrix, and custom ISA capabilities can be used to accelerate real‑world datacenter and AI workloads.
• How runtime, compiler, memory, and concurrency decisions impact performance at datacenter scale.
• How to build automated and AI‑assisted performance optimization workflows that continuously profile, analyze, modify, and benchmark software.
• How to influence future CPU architecture by connecting real workload behavior and software optimization opportunities to hardware design decisions.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export‑controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Voluntary Self-Identification

For government reporting purposes, we ask candidates to respond to the below self‑identification survey.Completion of the form is entirely voluntary. Whatever your decision, it will not be considered in the hiringprocess or thereafter. Any information that you do provide will be recorded and maintained in aconfidential file.

As set forth in Tenstorrent’s Equal Employment Opportunity policy,we do not discriminate on the basis of any protected group status under any applicable law.

If you believe you belong to any of the categories of protected veterans listed below, please indicate by making the appropriate selection.As a government contractor subject to the Vietnam Era Veterans Readjustment Assistance Act (VEVRAA), we request this information in order to measurethe effectiveness of the outreach and positive recruitment efforts we undertake pursuant to VEVRAA. Classification of protected categoriesis as follows:

A "disabled veteran" is one of the following: a veteran of the U.S. military, ground, naval or air service who is entitled to compensation (or who but for the receipt of military retired pay would be entitled to compensation) under laws administered by the Secretary of Veterans Affairs; or a person who was discharged or released from active duty because of a service‑connected disability.

A "recently separated veteran" means any veteran during the three‑year period beginning on the date of such veteran's discharge or release from active duty in the U.S. military, ground, naval, or air service.

An "active duty wartime or campaign badge veteran" means a veteran who served on active duty in the U.S. military, ground, naval, or air service during a war, or in a campaign or expedition for which a campaign badge has been authorized under the laws administered by the Department of Defense.

An "Armed forces service medal veteran" means a veteran who, while serving on active duty in the U.S. military, ground, naval, or air service, participated in a United States military operation for which an Armed Forces service medal was awarded pursuant to Executive Order 12985.