Firmware/Software Technology Lead

Astera Labs; San Jose (CA); On-site; USD 180,000 - 250,000; Full time

Benefits offered by this job

Flexible time off

Parental leave

401K

Retirement plans

Medical plans

Job summary

Astera Labs is hiring a Tech Lead Design Engineer to help architect and deliver the connectivity silicon powering AI clusters. You’ll own design execution on complex blocks, working at the cutting edge of PCIe, CXL, Ethernet, and interconnect technologies.

This high-impact role partners with architecture, verification, DFT, and physical design to take features from spec to silicon and create scalable design methodology for future tapeouts.

Qualifications

• Minimum 5+ years of digital design and at least one full chip tapeout.
• Strong PCIe, Ethernet, or similar high-speed interfaces and SoC integration.
• Experience with timing closure, CDC, lint, and low-power design techniques.
• Proficient in Verilog/SystemVerilog and RTL coding.
• Bachelor's degree required; MS/PhD preferred in EE/CE.

Responsibilities

• Own RTL design for blocks from microarchitecture through synthesis sign‑off.
• Develop synthesizable Verilog/SystemVerilog with strong PPA focus.
• Drive design reviews, lint, CDC, and timing closure to silicon‑ready quality.
• Partner with architecture to translate specs into implementation‑ready microarchitecture.
• Collaborate with verification on test plans, coverage, and bug triage.
• Work with DFT and physical design teams on scan, BIST, floorplanning, timing.
• Mentor junior engineers and contribute to design methodology and scripts.
• Debug complex pre‑silicon and post‑silicon issues across RTL, gate level, emulation.

Skills

Digital design

Verilog/SystemVerilog

RTL coding

Timing closure

Pre/post-silicon debugging

SoC integration

Mentoring

Tapeout experience

PCIe/CXL/Ethernet

Education

Bachelor's in EE/CE

MS/PhD in EE/CE

Tools

Synthesis flows

DFT/verification basics

Emulation

Formal verification

Job description

• Astera Labs is hiring a Tech Lead Design Engineer to help architect and deliver the connectivity silicon powering the world’s largest AI clusters. You’ll own design execution on complex blocks across our purpose-built products, working at the cutting edge of PCIe, CXL, Ethernet, and emerging rack-scale interconnect technologies
• This is a high-impact technical role at a hyper-growth company. You’ll partner closely with architecture, verification, DFT, and physical design teams to take features from spec to silicon, while contributing to the design methodology that scales with our roadmap. If you want to ship silicon that defines AI infrastructure, this is the team
• RTL Design & Implementation
• Own RTL design for assigned blocks from microarchitecture through synthesis sign-off
• Develop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA
• Drive design reviews, lint, CDC, and timing closure activities to silicon-ready quality
• Cross-Functional Execution
• Partner with architecture to translate specifications into implementation-ready microarchitecture
• Collaborate with verification on testplans, coverage closure, and bug triage
• Work with DFT and physical design teams on scan, BIST, floorplanning, and timing closure
• Technical Leadership & Quality
• Mentor junior engineers and contribute to design methodology, scripts, and best practices
• Debug complex pre-silicon and post-silicon issues across RTL, gate-level, and emulation environments
• Drive structured, data-driven design decisions in support of aggressive tapeout schedules

Benefits

• Flexible time off in the US
• Parental leave
• 401K
• Retirement and pension plans
• Competitive medical, dental and vision plans

Qualifications

• 5+ years of digital design experience, including at least one full chip from spec to tapeout
• Solid understanding of high-speed serial interfaces (PCIe, Ethernet, or similar) and SoC integration
• Hands-on experience with timing closure, CDC, lint, and low-power design techniques
• Strong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows
• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field
• MS or PhD in Electrical Engineering or Computer Engineering
• Experience with PCIe Gen5/Gen6, CXL, UALink, UCIe, or Ethernet MAC/PCS designs
• Familiarity with formal verification, emulation, or assertion-based methodologies
• Background in advanced process nodes (7nm, 5nm, or below)
• Strong debug skills across pre-silicon and post-silicon environments