Firmware Architect

TylSemi; San Jose (CA); On-site; USD 150,000 - 300,000; Full time

Job summary

TylSemi is seeking an experienced Firmware Engineer to lead the architecture of firmware and embedded software for chiplets. Ideal candidates will have over 12 years of embedded firmware development experience and strong technical leadership skills.

This role involves defining the architecture with Chip Architects, leading firmware development for silicon, and collaborating closely with customers. A BS/MS in Electrical Engineering or Computer Science is required, along with expertise in C programming and silicon validation.

Qualifications

• 12+ years of embedded firmware development experience.
• 5+ years of silicon-level bring-up and validation of high-speed interface IPs.
• Expert level C and assembly for embedded CPUs (RISC-V or Arm Cortex-M/R).

Responsibilities

• Own the firmware and embedded-software architecture for TylSemi chiplets.
• Lead firmware and host software development on emulation platforms.
• Set technical direction and roadmap for firmware systems.

Skills

Embedded firmware development

C programming

Debugging skills

Silicon-level bring-up

HW/SW co-simulation

Education

BS/MS in Electrical / Computer Engineering or Computer Science

Job description

Responsibilities

• Own the end‑to‑end firmware and embedded‑software architecture for TYLsemi chiplets.
• Define the firmware/hardware interface with Chip Architects, MCU subsystem architecture from the firmware perspective, and the chip’s debug interface and features.
• On‑die tasks: boot and secure boot, link sequencing, PCIe/CXL controller configuration and enumeration, address‑translation (NTB/ATT) setup, MSI‑X and AER handling, reset/FLR, power management, telemetry, and in‑field firmware update.
• Host‑side: kernel drivers, device‑virtualization/shim (synthetic PCIe device, VFIO‑mdev class), management libraries/APIs, and IOMMU coordination.
• Define the hardware/software boundary in architecture and RTL, own register maps and UCIe sideband/mailbox protocols.
• Create a unified firmware development and DV test flow with a single source of truth, and drive HW/SW co‑verification.
• Stay hands‑on through first silicon.
• Lead pre‑silicon firmware and host‑software development on emulation and virtual platforms, and post‑silicon bring‑up and debug.
• Build firmware engineering infrastructure: CI, automated and HIL testing, requirement traceability, secure‑development practices, and RAS/error‑handling strategy.
• Define firmware release, quality, and security criteria across products and customers.

Cross‑Functional & Customer Collaboration

• Serve as the technical bridge between firmware/software and architecture, RTL, DV, PHY/IP vendors, and program management.
• Engage directly with customers: compute‑SoC partners on PCIe/CXL enablement and integrators on firmware and management libraries.

Technical Leadership

• Set technical direction, roadmap, and clear subsystem ownership (boot/security, PCIe/CXL management, host drivers and virtualization, RAS/telemetry).

Qualifications

• BS/MS in Electrical / Computer Engineering or Computer Science.
• 12+ years of embedded firmware development, including at least 5 years of silicon‑level bring‑up and validation of high‑speed interface IPs.
• Working knowledge of DV and HW/SW co‑simulation/co‑verification flows, and the ability to define a unified firmware + DV test flow.
• Expert‑level C and assembly for resource‑constrained embedded CPUs (RISC‑V or Arm Cortex‑M/R class); strong debugging skills with JTAG/OpenOCD, trace, and logic analyzers.
• Hands‑on experience with HPC compute SoC firmware ecosystems—UEFI/BIOS bring‑up, ACPI table authoring, SMBus/I2C/MCTP platform management, VT‑d/IOMMU configuration on HPC platforms.
• Solid understanding of x86 server platform boot flow: PCIe enumeration, ROM interaction, and PCIe error‑recovery paths (AER, DPC).
• Experience with secure‑boot architectures, code‑signing flows, and OTA update mechanisms on embedded targets.
• Comfortable at the hardware‑software boundary: reading RTL, memory‑mapped register specs, and waveforms from simulation or a logic analyzer.

Preferred

• SPDM implementation experience.
• Familiarity with PLDM for firmware updates and platform telemetry.
• Exposure to chiplet packaging concepts (UCIe, EMIB, CoWoS) and multi‑die power‑sequencing.

Pay Range

150,000 - 300,000 USD per year (San Jose (HQ)).