Field-Programmable Gate Arrays Engineer

Radley James; Philadelphia (Philadelphia County); On-site; USD 225,000 - 275,000; Full time

Job summary

Radley James is seeking a Senior FPGA Engineer to design and build low-latency, hardware-accelerated trading systems. You will collaborate with quantitative researchers and trading teams to implement high-performance FPGA solutions.

Requirements include 8+ years FPGA/ASIC experience, VHDL/Verilog/SystemVerilog, and knowledge of Ethernet/PCIe interfaces. A degree in Electrical Engineering, CS, or Math is expected; experience in trading or related performance-critical fields is a plus.

Qualifications

• 8+ years FPGA or ASIC development experience.
• Strong expertise with VHDL, Verilog, or SystemVerilog.
• Knowledge of high-speed interfaces such as Ethernet and/or PCIe.
• Degree in Electrical Engineering, Computer Science, Mathematics, or a related technical discipline.
• Experience within trading, networking, telecommunications, datacentre infrastructure, aerospace, defence, or other performance-critical environments is welcome.

Responsibilities

• Architect, design, and develop high-performance FPGA solutions for latency-sensitive systems.
• Partner with researchers, software engineers, and trading teams to translate complex requirements into scalable hardware implementations.
• Own projects end-to-end, from architecture and design through deployment and production optimisation.
• Develop and enhance FPGA-based infrastructure supporting high-throughput, real-time trading environments.
• Continuously analyse and improve system performance in production.

Skills

FPGA design

Education

Electrical Engineering / CS / Math degree

Tools

VHDL/Verilog/SystemVerilog

Ethernet/PCIe interfaces

Job description

Philadelphia Area, PA

Base salary up to $250,000 + Significant performance Bonus

A leading quantitative trading firm is seeking a Senior FPGA Engineer to help design and build next-generation hardware-accelerated trading systems operating at the cutting edge of low-latency performance. This is an opportunity to work directly with quantitative researchers and trading teams to solve complex technical challenges that have an immediate impact on live trading strategies.

What you'll be doing:

• Architect, design, and develop high-performance FPGA solutions for latency-sensitive systems.
• Partner with researchers, software engineers, and trading teams to translate complex requirements into scalable hardware implementations.
• Own projects end-to-end, from architecture and design through deployment and production optimisation.
• Develop and enhance FPGA-based infrastructure supporting high-throughput, real-time trading environments.
• Continuously analyse and improve system performance in production.

What we're looking for:

• 8+ years of FPGA or ASIC development experience.
• Strong expertise with VHDL, Verilog, or SystemVerilog.
• Knowledge of high-speed interfaces such as Ethernet and/or PCIe.
• Degree in Electrical Engineering, Computer Science, Mathematics, or a related technical discipline.
• Experience within trading, networking, telecommunications, datacentre infrastructure, aerospace, defence, or other performance-critical environments is welcome.

Why consider this opportunity:

• Base salary up to $250,000.
• Significant annual bonus potential with strong upside tied to individual and firm performance.
• Work on some of the most technically challenging FPGA problems in the industry.
• Collaborate directly with elite engineers, researchers, and traders.
• Highly autonomous environment with ownership of solutions from concept through production.
• Access to cutting-edge hardware and infrastructure at substantial scale.

If you enjoy solving performance-critical engineering challenges and want your work to have a direct and measurable impact, we'd love to hear from you.