Engineer II - Verification

Microchip Technology Inc. (China); Chandler (AZ); Presencial; USD 120.000 - 160.000; Jornada completa

Descripción de la vacante

Microchip Technology Inc. in Chandler, AZ is seeking an Engineer II-Verification to join the dsPIC Microcontroller Business Unit's IP Verification Engineering team.

You will perform IP level verification, testbench architecture, modeling, simulation, and coverage with UVM or formal methods. Ideal candidates have 2.5–5 years in IP design verification, UVM/formal testbench development, and experience with AI/ML-based automation to improve verification quality and speed up debugging.

Formación

• Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, Physics, or related field with 2.5–5 years of verification experience.
• Experience in verification architecture, modeling, and simulation, UVM and Formal testbench development, coverage analysis, debugging, and lifecycle support.
• Proficiency in Python/Perl for automation and scripting.
• Strong understanding of digital design, RTL fundamentals, and ARM/SoC architectures.

Responsabilidades

• Architect, develop, and maintain UVM-based verification environments and/or Formal verification environments.
• Collaborate with architecture, designer, validation, and applications teams to verify IP and product requirements.
• Develop verification plans, test strategies, and testbenches.
• Create constrained-random tests, assertions, and coverage metrics; drive coverage closure.
• Develop Formal properties and proof results; drive Formal coverage closure.
• Configure, execute, and maintain UVM simulations and/or Formal regressions.
• Debug RTL and testbench failures; perform root-cause analysis with cross-functional teams.
• Leverage AI-assisted automation to improve verification quality and speed up debugging.

Conocimientos

IP verification

UVM

Formal verification

SystemVerilog

Python

Educación

Bachelor's degree in Electrical/Computer Engineering

Herramientas

UVM

SystemVerilog

Formal verification

Python

Perl

Descripción del empleo

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip's nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values ; we affectionately refer to it as the Aggregate System and it's won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Job Description

Join the dsPIC Microcontroller Business Unit, IP Verification Engineering team as Engineer II-Verification, doing IP level verification, testbench architecture, modeling, simulation, coverage, regression, formal or dynamic simulation (UVM tests), debugging, signoff evidence, and lifecycle support. This role is best suited for candidates with 2.5-5 years of relevant experience in IP design verification, testbench architecture, modeling, simulation, coverage, regression, formal or dynamic simulation, debugging, signoff evidence, and lifecycle support.

In this role, you will independently execute defined assignments and structured troubleshooting, partner with cross-functional teams (architecture, design, product development , validation, and application) across the USA, India, and other global corporate teams to deliver robust verification results, timely project execution, and continuous improvement.

Responsibilities

• Architect, develop, and maintain UVM based verification environments and/or Formal verification environments.
• Collaborate with architecture, designer, validation, and applications teams to verify IP and product requirements.
• Develop and maintain verification plans, test strategies and testbenches.
• Develop constraint random tests and testbench, assertions and coverage, analyze coverage metrics and drive coverage closure.
• Develop Formal properties, analysis proof results and drive Formal coverage closure.
• Configure, execute, and maintain UVM simulation and/or Formal regressions.
• Debug failures in RTL and testbench, perform root-cause analysis, and collaborate with design and architecture teams to resolve the defects.
• Leverage AI-assisted and machine-learning based automation to improve verification quality, accelerate development and debugging, and reduce verification cycle time.

Requirements/Qualifications

Minimum qualifications

Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, Physics, Engineering, or a related field with 2.5-5 years of relevant experience in design verification, UVM and/or Formal testbench architecture, modeling, simulation, coverage, regression, debugging, signoff evidence, and lifecycle support.

Qualified candidates should demonstrate verification architecture, modeling, and simulation, UVM and Formal testbench development, coverage analysis, structured debugging, AI/ML automation, technical documentation, and cross-functional influence.

Successful candidates are expected to demonstrate:

Employment stability, reliability, and sustained accountability in prior roles.

Effective teamwork and cross-functional collaboration.

Integrity and accuracy in representing qualifications, experience, and credentials.

Preferred Qualifications

• Hands-on experience with UVM-based simulation and/or Formal verification methodologies and tools.
• Strong proficiency in System Verilog language, constrained-random verification, assertions, and coverage.
• Experience developing and maintaining IP level and SoC level verification environments.
• Experience with simulation, regression execution, coverage analysis, debug, verification signoff, and lifecycle support.
• Experience with verification automation and scripting using Python or Perl.
• Experience with AI assisted technologies to improve verification productivity, quality, and driver faster coverage closure.
• Strong understanding of digital design concepts, RTL fundamentals, and ARM or common SoC architectures.

Travel Time

0% - 25%

Physical A