Embedded FPGA Engineer

Booz Allen Hamilton; McLean (VA); On-site; USD 86,800 - 198,000; Full time

Job summary

Booz Allen Hamilton is seeking an Embedded FPGA Engineer in McLean, Virginia. You will design, implement, and validate FPGA-based DSP systems on a SOSA/VPX platform, focusing on developing DSP algorithms and optimizing performance.

The ideal candidate will have 3+ years of experience with FPGA or SDR solutions, proficiency in languages like Python and C++, and an ability to work in Agile teams. Compensation ranges from $86,800 to $198,000 based on skills and experience.

Qualifications

• 3+ years of experience developing FPGA or SDR solutions.
• Ability to obtain a TS/SCI clearance.
• Experience using Agile processes and tools such as Jira.

Responsibilities

• Design and implement FPGA‑based DSP systems using HDL.
• Collaborate with teams to integrate FPGA designs with software.
• Test and validate FPGA designs for performance under constraints.

Skills

FPGA development

DSP algorithms

Python

C++

Agile processes

Verilog

VHDL

SystemVerilog

Linux/UNIX environments

Education

Bachelor's degree in Electrical Engineering

Bachelor's degree in Computer Engineering

Tools

Xilinx tools

Tcl scripting

Job description

Embedded FPGA Engineer

The opportunity to design, implement, and validate FPGA‑based digital signal processing (DSP) systems on a SOSA/VPX platform. This role focuses on developing DSP algorithms, integrating FPGA designs with software, and optimizing performance and resource usage.

What You Will Do:

• Design and implement FPGA‑based DSP systems using HDL, Vitis HLS, and modern FPGA toolchains.
• Develop and optimize DSP algorithms including filtering, detection, synchronization, modulation and demodulation, and transforms for high‑throughput, resource‑efficient hardware blocks.
• Collaborate with cross‑functional teams to integrate FPGA designs with software, firmware, and larger system architectures.
• Test, verify, and validate FPGA designs to ensure functional correctness, stability, and performance under real‑time constraints.
• Optimize designs for timing, area, power, and throughput using HLS directives and traditional FPGA workflows.
• Develop reusable hardware IP blocks to enable scalable DSP pipelines and accelerate future development.
• Maintain documentation such as design notes, block diagrams, interface definitions, user guides, and workflow references.
• Contribute to innovation by identifying new techniques and technologies that improve FPGA development efficiency and DSP performance.

You Have:

• 3+ years of experience developing FPGA or SDR solutions.
• Experience with Python, C++, MATLAB, or other languages used for modeling DSP algorithms.
• Experience using Agile processes and tools such as Jira or Confluence.
• Experience with FPGA design using Verilog, VHDL, SystemVerilog, or HLS and evaluation tools including simulation, synthesis, placement, timing analysis, implementation, and debug.
• Experience with Xilinx, Vitis, Vivado, or other FPGA ecosystems and scripting such as Tcl.
• Experience with Linux/UNIX development environments and scripting languages.
• Knowledge of digital design fundamentals, streaming architectures, pipelining, buffering, and datapath timing.
• Ability to read hardware schematics and work with lab equipment, including logic analyzers, oscilloscopes, and spectrum analyzers.
• Ability to obtain a TS/SCI clearance.
• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.

Nice If You Have:

• Experience implementing or prototyping DSP algorithms in hardware.
• Experience with SOSA/VPX systems.
• Experience developing HLS‑friendly algorithms and optimizing C/C++ code for hardware translation.
• Experience porting and adapting vendor RF transceiver reference designs to FPGA evaluation boards and custom platforms.
• Experience with RF testing.
• Experience with high‑speed digital interfaces such as AXI‑Stream, AXI‑Lite, DMA, and custom streaming buses.
• Experience with GPU acceleration, parallel computing, or high‑bandwidth data processing.
• Experience gathering requirements, shaping development roadmaps, or supporting Agile workflows.
• Experience with modern agentic engineering workflows, including AI‑driven automation for FPGA design, simulation, synthesis, or testing.
• Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

Clearance:

Applicants selected will be subject to a security investigation and may need to meet eligibility requirements for access to classified information.

Compensation

Projected compensation range: $86,800.00 to $198,000.00 per year. Salary is based on location, education, skills, and experience. The posting will close within 90 days from the posting date.

All qualified applicants will receive consideration for employment without regard to disability, status as a protected veteran, or any other status protected by applicable federal, state, local, or international law.