Embedded FPGA Engineer

Phase2 Technology; McLean (VA); On-site; USD 86,800 - 198,000; Full time

Benefits offered by this job

Eligible for benefit programs

Innovative work environment

Job summary

Phase2 Technology in McLean, Virginia, is looking for an Embedded FPGA Engineer to support the development and optimization of digital signal processing functions. The role involves designing and validating system components for RF signal processing applications using cutting-edge FPGAs.

The ideal candidate will have 3+ years of experience with FPGA development, strong knowledge of DSP algorithms, and a Bachelor's degree in Electrical or Computer Engineering. This position provides a competitive compensation range and opportunities for innovation in an Agile environment.

Qualifications

• 3+ years of experience developing FPGA or SDR solutions.
• Experience with FPGA design using Verilog, VHDL, or HLS.
• Ability to obtain a TS/SCI clearance.

Responsibilities

• Design FPGA-based DSP systems using HDL and Vitis HLS.
• Develop and optimize DSP algorithms for high-throughput.
• Collaborate to integrate FPGA designs with software and firmware.

Skills

FPGA development

Digital Signal Processing (DSP)

Collaboration

Python

C++

Agile methodologies

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Tools

Vitis

Vivado

Linux/UNIX

Job description

Embedded FPGA Engineer

Job Number: R0241391

Opportunity

We are seeking a motivated FPGA and software engineer to support the development, optimization, and deployment of digital signal processing (DSP) functions on a SOSA/VPX system. As a member of our engineering team, you will design, implement, and validate system components. You will contribute to building RF signal processing applications on an embedded platform with cutting‑edge FPGAs. You should be comfortable with writing HDL, using Vitis HLS, and be willing to learn new development acceleration tools outside of traditional workflows.

What You Will Do

• Design and implement FPGA‑based DSP systems using HDL, Vitis HLS, and modern FPGA toolchains.
• Develop and optimize DSP algorithms including filtering, detection, synchronization, modulation, demodulation, and transforms for high‑throughput and resource‑efficient hardware blocks.
• Collaborate with cross‑functional teams to integrate FPGA designs with software, firmware, and larger system architectures.
• Test, verify, and validate FPGA designs, ensuring functional correctness, stability, and performance under real‑time constraints.
• Optimize designs for timing, area, power, and throughput using HLS directives and traditional FPGA workflows.
• Develop reusable hardware IP blocks, enabling scalable DSP pipelines and accelerating future development.
• Maintain documentation, including design notes, block diagrams, interface definitions, user guides, and workflow references.
• Contribute to innovation by identifying new techniques and technologies that improve FPGA development efficiency, DSP performance, or overall system capability.

You Have

• 3+ years of experience developing FPGA or SDR solutions.
• Experience with Python, C++, MATLAB, or languages used for modeling DSP algorithms.
• Experience with Agile processes and tools, including Jira or Confluence.
• Experience with FPGA design using Verilog, VHDL, SystemVerilog, or HLS, and evaluation tools such as simulation, synthesis, fitting, timing analysis, implementation, and debugging.
• Experience with Xilinx, Vitis, Vivado, or FPGA development ecosystems and scripting such as Tcl.
• Experience with Linux/UNIX development environments and scripting languages.
• Knowledge of digital design fundamentals, streaming architectures, pipelining, buffering, and datapath timing.
• Ability to read hardware schematics and work with lab equipment, including logic analyzers, oscilloscopes, and spectrum analyzers.
• Ability to obtain a TS/SCI clearance.
• Bachelor's degree in Electrical Engineering or Computer Engineering.

Nice If You Have

• Experience implementing or prototyping DSP algorithms in hardware.
• Experience with SOSA/VPX systems.
• Experience developing HLS‑friendly algorithms and optimizing C/C++ code for hardware translation.
• Experience with porting and adapting vendor RF transceiver reference designs to FPGA evaluation boards and custom platforms.
• Experience with RF testing.
• Experience with high‑speed digital interfaces such as AXIStream, AXI‑Lite, DMA, and custom streaming buses.
• Experience with GPU acceleration, parallel computing, or high‑bandwidth data processing.
• Experience gathering requirements, shaping development roadmaps, or supporting Agile workflows.
• Experience with modern agile engineering workflows, including AI‑driven automation for FPGA design, simulation, synthesis, or testing.
• Master's degree in Electrical Engineering, Computer Engineering, or a related field.

Clearance

Applicants selected will be subject to a security investigation and may need to meet eligibility requirements for access to classified information.

Compensation

Full‑time and part‑time employees working at least 20 hours a week are eligible for Booz Allen's benefit programs. The projected compensation range for this position is $86,800.00 to $198,000.00 (annualized USD). This posting will close within 90 days from the posting date.

Equal Employment Opportunity

All qualified applicants will receive consideration for employment without regard to disability, status as a protected veteran or any other status protected by applicable federal, state, local, or international law.