A technology consulting firm in Herndon, Virginia, is seeking a Mid-Senior level Engineer for a long-term contract role requiring VHDL coding and experience with Xilinx FPGAs. This role involves hardware testing and static timing analysis in a collaborative Agile environment. Clearance is required for this position.
Qualifications
Experience with VHDL is required.
Proven track record in design packaging.
Understanding of EVM is necessary.
Responsibilities
Conduct testing on hardware.
Perform static timing analysis.
Utilize high-speed protocols effectively.
Skills
VHDL
HDL coding
Static timing analysis
High Level Synthesis (HLS)
High-speed protocols (PCIe, TCP/IP, Ethernet)
Xilinx FPGAs
Agile process
Tools
Vivado
Tools for compilation
Job description
Location: Herndon Virginia ( 5 Days onsite)
Duration: Long Term Contract
Clearance is required.
VHDL, HDL coding
tools for compilation
static timing analysis
testing on hardware
High Level Synthesis (HLS) with Vivado.
high-speed protocols (PCIe, TCP/IP, Ethernet)
Xilinx FPGAs and Vivado
proven track record
using tools to package design
Ethernet framing protocol, PCIe exp or they can demonstrate.
algorithm vs interface, Interface exp is required to proceed.