Electrical Engineer/ PCB Layout Designer

Russell Tobin; Fremont (CA); On-site; USD 83,000 - 88,000; Full time

Job summary

Russell Tobin is seeking a PCB Layout Designer for an on-site role in Fremont, CA. The candidate will perform PCB layout using Cadence Allegro and collaborate on schematic reviews and documentation to support design releases.

Requirements include 5+ years of PCB layout experience, experience with DRC/QC, and the ability to work with cross-functional teams. The role is five days a week onsite, 8:00 AM to 5:00 PM, with pay in the $60–$64 per hour range for 2+ years.

Qualifications

• Minimum 5 years of PCB layout experience.
• Experience with Cadence Allegro and related tooling.
• Familiarity with DRC/QC processes and documentation.
• Ability to support design release and cross-functional collaboration.
• Comfort working in an onsite, manufacturing-oriented environment.

Responsibilities

• Perform PCB layout using Cadence Allegro (80-90% of role).
• Collaborate with teams for schematic reviews, documentation, and updating BKM (Best Known Methods).
• Occasionally assist with cross-functional design efforts (~10–20%).
• Conduct and improve DRC and other QC measures to reduce post-release issues.

Skills

PCB layout

Cadence Allegro

Schematic reviews

Documentation

Design release

DRC/QC

Tools

Cadence Allegro

Job description

I’m Vishal from Russell Tobin. I’m reaching out regarding a PCB Layout Designer opportunity in Fremont, CA.

Position: PCB Layout Designer

Location: Fremont, CA – Onsite 5 days/week

Schedule: Monday–Friday, 8:00 AM–5:00 PM

Pay: $60/hr- $64/hr

Duration: 2+ years

Primary Tool: Cadence Allegro

Experience: 5+ years of PCB layout experience

The role is primarily focused on PCB layout using Cadence Allegro, along with schematic reviews, DRC/QC, documentation, and design-release support. Experience with digital, analog, and power boards is preferred. Semiconductor experience is a plus, but candidates from aerospace, medical, or other high-tech industries are welcome.

Role Overview

• The position is primarily a PCB Layout Designer role.
• Role is on-site 5 days a week at Fremont Lam campus.

Primary Responsibilities

• Perform PCB layout work using Cadence Allegro (80-90% of role).
• Collaborate with other teams for schematic reviews, documentation, and updating BKM (Best Known Methods).
• Occasionally assist with cross-functional design efforts (~10–20% of time).
• Conduct and improve Design Rule Checks (DRC) and other quality control measures to reduce post-release errors.

Tools & Technical Details

• CAD Tool: Cadence Allegro (currently version 22.1, previously 17.4).
• Must have strong experience with Allegro; ok if they have only used previous versions
• No flex cable designs: focus is on traditional PCB types.
• Boards range from 2 to 40 layers, including digital, analog, and power circuits.
• Common connectors: D-Subs (9-pin, 15-pin), Ethernet (hardened), and industrial-grade coaxials.

Experience Requirements

• Minimum: 5 years of PCB layout experience.
• Open to: Senior-level designers (15–20+ years).
• Candidates nearing retirement are acceptable but must commit to at least 2 years.
• Industry background is flexible — semiconductor experience is not required but is preferred . Aerospace, medical, or other high-tech PCB experience is acceptable.
• Primary Challenge: Improving design quality and minimizing rework.
• Goal: Ensure thorough QC and DRC before release to avoid client-reported issues.
• Department is focused on releasing boards "right the first time

Russell Tobin is an equal opportunity employer. We do not discriminate on the basis of the race, religious creed, color, national origin, ancestry, physical disability, mental disability, reproductive health decision making, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age, sexual orientation, veteran or military status, or any other characteristic protected by applicable federal, state, or local law.

Russell Tobin is a Fair Chance employer. We consider all qualified applicants, including those with criminal histories, in a manner consistent with applicable state and local Fair Chance laws and ordinances, including, the California Fair Chance Act and all applicable local Fair Chance ordinances.

Accommodations

We are committed to providing reasonable accommodations to applicants and employees with disabilities. If you require a reasonable accommodation to participate in the application or interview process, or to perform the essential functions of this role, please contact us.

Only applicable for San Francisco Candidates:

Under the San Francisco Lactation in the Workplace Ordinance, we will provide written notice of lactation accommodation rights, and this notice will automatically be given upon hiring, any inquiry of parental leave or lactation accommodation.