Electrical Design and Analyst Engineer 4

Boeing Future of Flight; Mountain View (CA); On-site; USD 103,320 - 110,208; Part time

Benefits offered by this job

Medical

Dental

Vision

401K

Job summary

A leading aerospace company is seeking an Electrical Design and Analyst Engineer to work in Mountain View, CA. This contract role focuses on ASIC/FPGA verification, requiring expertise in SystemVerilog and a Bachelor's degree in a relevant field. You will be responsible for writing test benches and collaborating with hardware teams. The position offers competitive pay rates of $75 to $80 per hour and optional benefits such as medical and dental coverage.

Qualifications

• Bachelor’s degree in EE, CE, CS, or related field (or equivalent experience).
• Experience with ASIC/FPGA verification using SystemVerilog and UVM.
• Comfortable in Linux and using scripting tools.

Responsibilities

• Write SystemVerilog/UVM test benches to verify ASICs and FPGAs.
• Develop self-checking, reusable UVM components: drivers, monitors, scoreboards, sequencers.
• Collaborate with system and hardware teams to capture requirements and debug issues.

Skills

ASIC/FPGA verification using SystemVerilog and UVM

Building self-checking test benches

Scripting tools (Python/Perl/Make)

Linux operating system

Education

Bachelor’s degree in EE, CE, CS, or related field

Job description

Electrical Design and Analyst Engineer 4 (Contract)

Mountain View, CA, United States (On-site)

Contract (1 year)

Published 1 day ago

On hold

This posting is for a contract assignment and is not a full‑time employment offer with Boeing. Candidates selected for roles will be employed as contract workers through a Boeing approved 3rd party for the duration of the specified project.

Regular and predictable attendance is required

Work statement is a non‑managerial role, non‑leadership role.

ASIC/FPGA Verification Engineer (UVM / SystemVerilog) Location: Mountain View, CA

Team: Boeing Electronic Products — ASICs & FPGAs for Space, Avionics, and Defense

Position Responsibilities

• Write SystemVerilog/UVM test benches to verify ASICs and FPGAs.
• Develop self‑checking, reusable UVM components: drivers, monitors, scoreboards, sequencers.
• Build functional coverage models and close code coverage gaps.
• Create tests that verify DSP and third‑party IP integration.
• Run simulations, linting, CDC checks, static timing checks, and gate‑level regressions.
• Use scripting (Python/Perl/Make) and revision control (git/svn) to automate flows.
• Support FPGA bring‑up, hardware emulation/prototyping, and hardware integration tests.
• Collaborate with system and hardware teams to capture requirements and debug issues.

Required Skills

• Bachelor’s degree in EE, CE, CS, or related field (or equivalent experience).
• Experience with ASIC/FPGA verification using SystemVerilog and UVM.
• Ability to build self‑checking test benches and use object‑oriented SV features.
• Familiarity with functional coverage and code coverage closure.
• Comfortable in Linux and using scripting tools.

Preferred Skills

• 2+ years (Associate) or 5+ years (Experienced) verification experience.
• Experience with hardware emulators (e.g., Palladium) and FPGA prototyping.
• Knowledge of high‑speed SerDes (PCIe, Ethernet, JESD204C).
• Experience with SVA (SystemVerilog Assertions) and RTL‑to‑GDS flows.
• Familiar with space/radiation mitigation techniques is a plus.

Pay Rate Range

Min Pay Rate $75

Max Pay Rate $80

Currency USD

Unit hourly

Benefits Information

• Optional Benefits: Medical, Dental, Vision, 401K

Tundra Technical Solutions is among North America’s leading providers of Staffing and Consulting Services. Our success and our clients’ success are built on a foundation of service excellence. We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic. Qualified applicants with arrest or conviction records will be considered for employment in accordance with applicable law, including the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act. Unincorporated LA County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: client provided property, including hardware (both of which may include data) entrusted to you from theft, loss or damage; return all portable client computer hardware in your possession (including the data contained therein) upon completion of the assignment, and; maintain the confidentiality of client proprietary, confidential, or non-public information. In addition, job duties require access to secure and protected client information technology systems and related data security obligations.