Edge AI Vision DFT Engineer (RTL to ATE)

VisLab (an Ambarella Inc. company); Kentucky; On-site; USD 140,000 - 150,000; Full time

Benefits offered by this job

RSU grants

Annual RSU grants

Competitive benefits

Job summary

Ambarella, a world leader in edge AI semiconductors, is seeking an experienced DFT engineer to join our team in Kentucky. You will drive DFT implementation from RTL to post-production for a multi-million gate Computer Vision SoC, delivering robust patterns and test strategies.

Collaborate with design and product engineering, verify DFT via timing simulations, and support ATE bring-up and silicon production.

Qualifications

• MS in Electrical / Computer Engineering or BS with 1-5 years in DFT implementation.
• Knowledge of DFT fundamentals.
• Knowledge of Logic design and timing.
• Knowledge of Verilog and Python.
• Knowledge of Mentor Tessent tools is a plus.
• Knowledge of scan diagnostics is a plus.

Responsibilities

• DFT implementation from RTL to Post-Production for a multi-million gate Computer Vision SoC.
• Analyze clocking and implement clock control structure for at-speed scan testing.
• Develop/Generate high-quality scan and mbist patterns.
• DFT Verification (including post place-and-route timing simulations).
• Work with Product Engineering team to bring up scan & mbist patterns on ATE.
• Support silicon production activities including failure diagnosis and test optimization.

Skills

Knowledge of DFT fundamentals

Knowledge of logic design and timing

Verilog

Python

Scan diagnostics

Education

MS in Electrical / Computer Engineering

BS in Electrical/Computer Engineering with 1-5 years experience

Tools

Mentor Tessent tools

MBIST tooling

Job description

Ambarella, a world leader in edge AI semiconductors, is seeking an experienced DFT engineer to join our team in Kentucky. You will drive DFT implementation from RTL to post-production for a multi-million gate Computer Vision SoC, delivering robust patterns and test strategies.

Collaborate with design and product engineering, verify DFT via timing simulations, and support ATE bring-up and silicon production.