EDA Design Flow Development Engineer

Intel Corporation; Santa Clara (CA); Hybrid; USD 142,000 - 269,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Hybrid work model

Job summary

Intel Corporation in Santa Clara, CA, is seeking an EDA CAD / Tool Flow Development Engineer to advance transistor-level EM/IR analysis flows across new technologies. You will contribute to automation, silicon correlation, and reliability verification, partnering with design and signoff teams.

The role requires strong SPICE-based verification and scripting skills in a collaborative, hybrid work environment. Ideal for engineers with deep EMI/IR experience.

Qualifications

• EM/IR reliability concepts including electromigration and power drop.
• Experience with Redhawk/Totem tools.
• 6+ years of experience with a Bachelor's degree; or 4+ years with a Master's; or 2+ years with a PhD.

Responsibilities

• Develop and maintain transistor-level EM/IR analysis flows for custom IPs and advanced-node designs.
• Automate power integrity analysis workflows and validate silicon correlation with design teams.
• Collaborate with circuit, physical, package, reliability and signoff teams to ensure scalable methodologies.

Skills

EM/IR reliability concepts

SPICE simulation

Linux scripting & automation

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Redhawk/Totem

Job description

The Role and Impact

Join Intel in shaping the future of technology. As an EDA Tools Hardware Engineer, you will play a pivotal role in enabling groundbreaking innovations that power Intel's leadership in semiconductor design and manufacturing. We are seeking an experienced EDA CAD / Tool Flow Development Engineer to develop and maintain transistor-level electromigration (EM) and IR drop analysis flows for custom IPs, embedded memories, SRAMs, analog/mixed-signal interfaces, and high-performance custom macros across advanced semiconductor technologies. This role focuses on CAD methodology, automation infrastructure, power integrity analysis flows, and silicon correlation for transistor-level reliability verification. The engineer will work closely with circuit design, physical design, package, reliability, and signoff teams to enable scalable and accurate EM/IR analysis methodologies for advanced-node designs. The ideal candidate has strong expertise in transistor-level power integrity analysis, SPICE-based verification, parasitic-aware reliability modeling, and automation development using industry-standard EM/IR signoff tools.

Minimum Qualifications

• Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field, and 6+ years of experience; 4+ years of experience with a Master's degree; or 2+ years of experience with a PhD.
• EM/IR reliability concepts (Electromigration, and Power Drop).
• Experience with Redhawk/Totem tools.

Preferred Qualifications

• CMOS circuit operation
• Power delivery networks
• SPICE simulation
• Parasitic extraction fundamentals
• Advanced-node design challenges
• Transistor-level power integrity analysis flows
• Scripting and automation skills in Linux environments

Job Details

• Job Type: Experienced Hire
• Shift: Shift 1 (United States of America)
• Primary Location: US, California, Santa Clara
• Additional Locations: US, California, Folsom, US, Oregon, Hillsboro, US, Texas, Austin

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

• We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Salary Range

Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD

Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.

Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.