Senior Density Fill Development Engineer

Intel Corporation; Hillsboro (OR); On-site; USD 129,000 - 245,000; Full time

Benefits offered by this job

Stock bonuses

Competitive pay

Benefits programs (health, retirement,

Find out more about Intel benefits

Job summary

Intel Corporation in Hillsboro, Oregon is seeking an experienced EDA Tools Software Engineer to design, develop, test, and debug software tools supporting advanced process technologies. The role focuses on density fill, PDKs, and tool integration within diverse design methodologies.

The position requires strong Unix/Linux skills, collaboration with cross-functional teams, and a track record in physical verification tooling. Hybrid work model and competitive benefits accompany this opportunity.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 8+ years of experience, Master's with 5+ years, or PhD with 2+ years.
• 5+ years of hands-on experience with a physical verification platform (Calibre, ICV, or Pegasus).
• 3+ years of experience developing or debugging physical verification rule decks using SVRF, TVF, PXL, or PVL/PVTCL.

Responsibilities

• Design, develop, and debug Fill components of Process Design Kits (PDKs).
• Provide algorithmic solutions to address density deficiencies and manufacturability using Calibre/ICV/Pegasus.
• Collaborate with process developers, rule owners, and end users to define requirements and implement solutions.

Skills

Unix/Linux

Analytical skills

Cross-functional collaboration

Leadership

Education

Bachelor's degree in EE/CE or related field

Master's degree

PhD

Tools

Cadence Virtuoso

Synopsys Custom Designer

Calibre

ICV

Pegasus

Job description

Job Details: Job Description:

Join Intel's Design Technology Platform (DTP) organization and become an integral part of a highly skilled team driving the development of cutting-edge technologies. As an EDA Tools Software Engineer, you will design, develop, test, and debug software tools and methodologies that directly support Intel's hardware product design and manufacturing processes. Your work will enable design teams to innovate faster, meet complex manufacturability constraints, and deliver industry-leading products to market. By contributing to Intel's advanced process technologies, you will play a pivotal role in achieving leadership in design automation and fostering a culture of innovation. In this role, you will have a unique opportunity to make a lasting impact by enabling Intel's success in the competitive semiconductor landscape.

Key Responsibilities

• Design, develop, and debug Fill components of Process Design Kits (PDKs),
• Provide algorithmic solutions using tools such as Calibre, ICV, and Pegasus to address density deficiencies and ensure manufacturability compliance.
• Collaborate with process developers, design rule owners, and end users to define requirements and implement state-of-the-art solutions.
• Automate workflows to enhance efficiency, accuracy, and deployment across design teams.
• Develop comprehensive test cases and systems to validate software tools and ensure seamless integration with various design methodologies.
• Innovate and drive advancements in EDA tools and methodologies to meet the evolving needs of Intel's technology ecosystem.
• Partner with cross-functional teams and external EDA vendors to define and implement new tool features and methodologies.
• Maintain documentation, including training materials and user guides, to support customers and ensure robust deployment.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 8+ years of experience, Master's degree with 5+ years of experience, or PhD with 2+ years of experience.
• Minimum 5 years of hands-on experience with at least one industry-standard physical verification platform (Calibre, ICV, or Pegasus), including methodology development, rule deck debugging, or production deployment.
• 3+ years of direct experience developing, maintaining, or debugging physical verification rule decks using SVRF, TVF, PXL, or PVL/PVTCL for DRC, density, or fill verification applications.
• Solid understanding of semiconductor device physics, process technology, and design rules.
• Experience in developing algorithmic solutions for physical design challenges in advanced manufacturing nodes.
• Strong knowledge of Unix/Linux platforms and computing environments.

Preferred Qualifications

• 5+ years of hands-on experience developing, deploying, or supporting density fill methodologies for semiconductor technologies at 16nm and below, including ownership of fill rule implementation, density compliance, or manufacturability optimization.
• Experience with advanced physical verification techniques, including DRC, and density/fill modules.
• Industry experience with other foundry technologies in this domain is strongly desirable.
• Familiarity with custom layout tools such as Cadence Virtuoso or Synopsys Custom Designer.
• Deep understanding of technology scaling challenges and their impact on physical design rules.
• Proven track record of collaborating across multiple internal and external teams to deliver optimal solutions.
• Exceptional analytical and problem-solving skills with the ability to address cross-disciplinary challenges.
• Strong written and verbal communication skills, with the ability to present complex technical concepts clearly.
• Leadership experience driving innovation, process improvements, or cross-functional initiatives.
• Strong preference for candidates with experience from semiconductor foundries, advanced packaging organizations (OSATs), integrated device manufacturers (IDMs), or EDA vendors, where they have contributed to physical verification, density-fill methodology development, process design kits (PDKs), or manufacturing-driven design solutions.

Job Type

Experienced Hire

Shift

Shift 1 (United States of America)

Primary Location

US, Oregon, Hillsboro

Additional Locations

US, Arizona, Phoenix, US, California, Santa Clara, US, Texas, Austin

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

• competitive pay
• stock bonuses
• benefit programs which include health, retirement, and vacation
• Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US

$128,880.00-245,160.00 USD

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Additional Information

• * Job posting details (such as work model, location or time type) are subject to change.
• * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Intel’s official careers website. Find your next job and take on projects that shape tomorrow’s technology.

Benefits Internships Life at Intel Locations Recruitment Process