EDA and CAD Lead Engineer / Manager

AttoTude; United States; Remote; USD 140,000 - 200,000; Full time

Benefits offered by this job

Stock options plan

Paid time off

Health benefits

Job summary

AttoTude inc. seeks an experienced EDA/CAD lead engineer to guide CMOS IC implementation from concept to production. You will join the experience design and layout team to drive floorplanning, IP integration, and tape‑outs for mixed‑signal chips.

You will work with analog/mixed‑signal, digital, and RF teams, performing LVS/DRC checks and collaborating across functions to deliver high‑quality designs on schedule. Remote role with occasional Bay Area travel.

Qualifications

• 5+ years hands-on CMOS IC implementation in multiple process techs.
• Experience with Cadence and related EDA tools.
• Proven tape-out support across projects.
• Tcl, Python, Perl, Makefile, and shell scripting required.

Responsibilities

• Floor planning and IP integration for mixed‑signal ICs.
• Pad ring creation and layout for high‑performance designs.
• Collaborate with RF/Mixed Signal, Hardware, Firmware, and Software teams.
• Perform LVS/DRC checks and issue fixes.
• Oversee integration of Digital/RF/mmWave blocks into top level.
• Support design tape-outs with cross‑functional teams.
• Stay current with wideband high‑speed IC design trends.

Skills

CMOS/FinFET expertise

Cadence tools

Tape-out experience

Scripting (Tcl/Python)

Education

Bachelors in EE/CS

Cadence digital layout training

Tools

Virtuoso

Calibre

Voltus

Job description

We are seeking an experienced EDA/CAD lead engineer to join our growing team. In this role, you will be part of the experience design and layout team to develop cutting‑edge mixed‑signal ICs. You will be involved in the technical aspects of the ASIC design and development, from concept through to production. This is a hands‑on technical position that requires in‑depth technical expertise, and the ability to work in a team of highly experienced engineers to accomplish the goals.

Key Responsibilities:

• Floor planning, IP integration

• Pad Ring creation

• Work with analog/mixed‑signal designers for high‑performance layout integration

• Work with digital designers for DFT/ATPG/Scan logic integration

• Perform LVS/DRC checks and fix issues

• Integration of Digital/RF/mmWave blocks into IC Top Level

• Collaborate with cross‑functional teams to ensure timely project execution and design tape‑outs

• Stay updated with the latest trends and technologies in wideband high speed IC design and apply them to improve project outcomes

• Occasional travel to the Bay Area (<20%) for remote position

Qualifications:

• 5+ years of hands‑on experience in CMOS (bulk and advanced FinFET) IC implementation in multiple process technologies

• Strong experience with Cadence (and various EDA) tools is required (Virtuoso, Calibre, Voltus)

• Experience in multiple dedicated tape‑out support is required

• Scripting language experience in Tcl, Python, Perl, Makefile, and shell scripts are required

Education:

• Formal Cadence digital layout training or certification is required

• Bachelor’s degree in electrical engineering, computer science or a related field is preferred

Preferred Skills:

• Experience with CMOS, and/or SiGe Process Development Kits

• Experience working on a multidisciplinary team with RF/Mixed Signal, Hardware, Firmware, and Software engineers

• Strong communication and teamwork skills

• Experience working in fast‑paced environments with a strong track record of delivering high‑quality designs on time.

Benefits:

• Competitive salary

• Stock options plan

• Paid time off

• Health benefits

Annual Salary Range

$140,000—$200,000 USD