DRAM Process Integration Engineer: Yield & Scale

Micron Technology, Inc; Boise (ID); On-site; USD 90,000 - 120,000; Full time

Benefits offered by this job

Medical plans

Dental plans

Vision plans

Paid time off

Paid holidays

Job summary

Micron Technology, Inc. is seeking a Device Process Integration Engineer with CMOS expertise to drive DRAM process integration in manufacturing and support yield ramps.

You will analyze electrical data, identify yield detractors, and collaborate with cross‑functional teams to improve device performance. Responsibilities include optimizing process flows, monitoring production, and ensuring compliance with specifications while advancing advanced DRAM technologies through AI‑assisted analytics and

Qualifications

• Master's degree in Electrical Engineering, Materials Science, or related field (or equivalent experience).
• CMOS technology and semiconductor manufacturing fundamentals experience.
• Experience with statistical data analysis and problem-solving methodologies.

Responsibilities

• Enable next generation DRAM technologies in manufacturing and support yield ramp activities.
• Analyze electrical and inline process data to identify yield detractors and improvements.
• Optimize process integration flows to enhance yield, performance, and manufacturability.
• Monitor manufacturing performance and ensure process specifications meet requirements.

Skills

CMOS technology

Statistical data analysis

AI‑assisted analytics

Yield engineering

Education

Master's degree in Electrical Engineering, Materials Science, or related field

Tools

CMP

Thin films

Etch

Photolithography

Job description

Micron Technology, Inc. is seeking a Device Process Integration Engineer with CMOS expertise to drive DRAM process integration in manufacturing and support yield ramps.

You will analyze electrical data, identify yield detractors, and collaborate with cross‑functional teams to improve device performance. Responsibilities include optimizing process flows, monitoring production, and ensuring compliance with specifications while advancing advanced DRAM technologies through AI‑assisted analytics and