Digital IC Design Lead (PMIC & Mixed-Signal)

Celera Semiconductor; San Francisco (CA); Presencial; USD 180.000 - 240.000; Jornada completa

Descripción de la vacante

Celera Semiconductor is seeking a Digital Design Lead to own the digital architecture, RTL implementation, and system integration of PMICs in a fast-paced environment.

The role requires 10+ years in digital IC design with PMIC/Mixed-Signal focus, strong SystemVerilog/Verilog RTL skills, and experience with Cadence and Synopsys toolchains. Lead a team through multiple successful tape-outs and collaborate with analog design on top-level integration.

Formación

• Bachelor’s or Master’s degree in Electrical or Computer Engineering.
• 10+ years in digital IC design, with at least 5 years focused on PMIC or Mixed-Signal products.
• Proficiency in SystemVerilog/Verilog RTL coding for synthesis.
• Hands-on experience with digital control loops for power converters.
• Familiarity with Cadence Genus/Tempus or Synopsys DesignCompiler/PrimeTime toolsets.
• Process knowledge: BCD nodes and Clock Domain Crossing in mixed-signal environments.

Responsabilidades

• Define and document the micro-architecture for PMIC digital cores, including state machines for power sequencing and fault handling.
• Lead digital-on-top integration with analog leads to define interfaces and digital control loops.
• Design high-quality, low-power RTL for PWM controllers, interfaces (I2C, SPI, PMBus, I3C), and OTP/MTP memory controllers.
• Oversee insertion of scan chains, ATPG, and BIST to ensure high production yield and test coverage.
• Develop verification plans and drive Mixed-Signal simulations (Verilog-AMS/Real Number Modeling) to validate hardware–software interactions.
• Lead the synthesis, LEC, and STA flows to ensure the digital logic meets performance targets across process corners.

Conocimientos

Digital Architecture

RTL Design

SystemVerilog/Verilog

PMIC

Mixed-Signal

DFT

Verification

Synthesis/STA

Educación

Electrical or Computer Engineering degree

Herramientas

Cadence Genus/Tempus

Synopsys DesignCompiler/PrimeTime

Descripción del empleo

As the Digital Design Lead, you will be responsible for the digital architecture, RTL implementation, and system integration of Power Management ICs.

Key Responsibilities

• Digital Architecture:Define and document the micro-architecture for PMIC digital cores, including state machines for complex power-up/down sequencing and fault handling.
• Mixed-Signal Integration:Lead the "digital-on-top" or "analog-on-top" integration, working closely with analog leads to define interfaces and digital control loops.
• RTL Design & Implementation:Design high-quality, low-power RTL usingSystemVerilogorVerilogfor functions like PWM controllers, serial interfaces (I2C, SPI, PMBus, I3C), and OTP/MTPmemory controllers.
• Design for Test (DFT):Oversee the insertion of scan chains, ATPG, and BIST to ensure high production yield and test coverage.
• Verification Strategy:Develop verification plans and drive Mixed-Signal simulations (Verilog-AMS/Real Number Modeling) to validatehardware-software interactions.
• Synthesis & Timing:Lead the synthesis, Logic Equivalency Checking(LEC), and Static Timing Analysis (STA) flows to ensure the digital logicmeets performance targets across all process corners.

Required Qualifications

• Education:Bachelor’s or Master’s degree in Electrical or Computer Engineering.
• Experience:10+ years in digital IC design, with at least 5 years focused onPMICorMixed-Signalproducts.
• Technical Expertise:
• Proficiency inSystemVerilog/VerilogRTL coding for synthesis.
• Hands-on experience withdigital control loopsfor power converters
• Familiarity withCadence(Genus/Tempus) orSynopsys(DesignCompiler/PrimeTime) toolsets.
• Process Knowledge:Experience withBCDprocess nodes and understanding of Clock Domain Crossing (CDC) in mixed-signal environments.

Preferred Skills

• Knowledge offirmware/softwareinteractions for programmable PMICs.
• Proven ability to lead and mentor a team of digital designers through multiple successful tape-outs.