RTL Design Engineer

Synopsys Inc; Boxborough (MA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Comprehensive benefits package

Competitive compensation

Job summary

Synopsys Inc. is seeking a highly experienced digital design engineer to lead RTL and PHY architecture for high-speed interfaces such as DDRIO and UCIe.

You will own ASIC design cycles from concept to implementation, mentor engineers, and collaborate with verification, physical design, and system teams to deliver scalable silicon solutions. You will influence architectural decisions, optimize for performance, power, area, and drive complex IP development across SERDES and DDR subsystems,

Qualifications

• BS in Electrical Engineering, Computer Engineering, or related field (12+ years of experience) OR MS with 10+ years of experience.
• Strong experience in ASIC RTL design and digital logic development.
• Expertise in PHY design, DDRIO, UCIe, SERDES, or related high-speed interfaces.
• Solid understanding of the complete SoC design cycle, from architecture to implementation.
• Experience with design verification methodologies and hardware debugging.

Responsibilities

• Architect, design, and develop high-performance digital logic for PHY, DDRIO, and UCIe-based solutions.
• Define and implement RTL architectures with verification, physical design, and system teams.
• Drive chip- and block-level design activities through all ASIC development phases.
• Optimize designs for performance, power, area (PPA), and scalability.
• Develop and evaluate complex physical IP solutions, including SERDES and DDR subsystems.
• Review designs and mentor engineers to ensure technical excellence.
• Collaborate with cross-functional teams to deliver silicon solutions on schedule.

Skills

ASIC RTL design

Digital logic development

PHY design

DDRIO

UCIe

SERDES

SoC design cycle

Design verification

Hardware debugging

Communication skills

Education

BS in Electrical Engineering or Computer Engineering

MS in EE/CE (optional)

Tools

EDA tools

Job description

We Are

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, enabling everything from self-driving cars to AI-powered systems. We lead in chip design, verification, and IP integration, empowering innovators to create high-performance silicon and software solutions. Join us and help shape the future of technology.

You Are

A highly experienced digital design engineer with deep expertise in PHY architecture and RTL development. You bring a strong foundation in high-speed interface technologies such as DDR and UCIe, combined with hands-on experience delivering complex ASIC designs from concept through implementation. You thrive in collaborative environments, enjoy solving challenging technical problems, and are passionate about developing innovative semiconductor solutions.

What You'll Be Doing

• Architect, design, and develop high-performance digital logic for PHY, DDRIO, and UCIe-based solutions.
• Define and implement RTL architectures while working closely with verification, physical design, and system teams.
• Drive chip- and block-level design activities through all phases of the ASIC development cycle.
• Optimize designs for performance, power, area (PPA), and product scalability.
• Develop and evaluate complex physical IP solutions, including SERDES and DDR subsystems.
• Review designs and mentor engineers to ensure technical excellence and development best practices.
• Collaborate with cross-functional teams to deliver high-quality silicon solutions on schedule.

The Impact You Will Have

• Enable next-generation high-speed connectivity solutions used in advanced semiconductor products.
• Influence architectural decisions that improve performance, power efficiency, and scalability.
• Contribute to industry-leading PHY and interface IP development.
• Drive innovation that strengthens Synopsys' leadership in semiconductor design solutions.
• Support technical growth across the engineering organization through collaboration and mentorship.

What You'll Need

• BS in Electrical Engineering, Computer Engineering, or related field with 12+ years of relevant experience, or MS with 10+ years of experience.
• Strong experience in ASIC RTL design and digital logic development.
• Expertise in PHY design, DDRIO, UCIe, SERDES, or related high-speed interface technologies.
• Solid understanding of the complete SoC design cycle, from architecture through implementation.
• Experience with design verification methodologies and hardware debugging.
• Strong problem-solving, analytical, and communication skills.

Preferred Qualifications

• Experience developing complex IPs for advanced process technologies.
• Familiarity with low-power design techniques and clocking architectures.
• Experience mentoring engineers and leading technical projects.
• Knowledge of industry-standard EDA tools and design methodologies.

Who You Are

• A collaborative engineer who enjoys working across multidisciplinary teams.
• A self-starter who can drive complex projects with minimal supervision.
• A creative problem solver with attention to detail and a commitment to quality.
• An effective communicator who can simplify complex technical concepts.
• A mentor who enjoys helping others grow and succeed.

The Team You'll Be A Part Of

You will join a talented team responsible for developing next-generation PHY and interface IP solutions. The team works across architecture, RTL design, verification, and implementation to deliver industry-leading technologies that enable the world's most advanced semiconductor products.

Rewards and Benefits

Synopsys offers a comprehensive and competitive benefits package designed to support your health, wellbeing, and financial future.