Digital ASIC Design Engineer for High-Speed Interfaces

Qualcomm; San Diego (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

An innovative firm is seeking a talented senior ASIC digital designer to join their mixed-signal IP design team. This role involves developing high-speed interfaces crucial for AI/ML, computing, and automotive sectors. You will define standards, collaborate with cross-functional teams, and own RTL design, ensuring power and performance optimization. With a commitment to equal opportunity, this position offers a competitive salary, comprehensive benefits, and a chance to work on cutting-edge technologies in a dynamic environment. If you're passionate about ASIC design and eager to make an impact, this opportunity is perfect for you.

Benefits

Annual bonus

RSU grants

Comprehensive benefits package

Work-life balance support

Qualifications

• 5+ years of experience in micro-architecture and RTL design.
• Proficiency with ASIC design tools and low-power digital design.

Responsibilities

• Define high-speed interface PHYs and collaborate on architecture definitions.
• Design and optimize microarchitecture of IP blocks.

Skills

Micro-architecture design

RTL design

ASIC design tools

Power optimization

Verification planning

Education

Master's in Electrical Engineering

Bachelor's in Electrical Engineering

Tools

Design Compiler

PrimeTime

ModelSim

Job description

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group > ASICS Engineering

General Summary:

Qualcomm's mixed-signal IP design team is seeking talented senior ASIC digital designers to develop high-speed interfaces such as SerDes, DDR, and Die-to-Die technologies, crucial for products in AI/ML, computing, and automotive sectors.

This position is located in San Diego only.

Responsibilities:

• Define standards and proprietary high-speed interface PHYs.
• Collaborate with cross-functional teams on architecture definitions.
• Design, document, and develop microarchitecture of IP blocks.
• Own RTL design and implement specifications.
• Optimize power, performance, and area using computer architecture techniques.
• Utilize ASIC front-end tools for design and verification tasks.
• Create detailed design specifications and verification plans.
• Coordinate with physical design team for implementation.
• Work with verification teams to define test plans and debug.
• Assist testing teams during silicon bring-up.

Minimum Qualifications:

• Master's degree in Electrical Engineering, Computer Engineering, or related fields.
• At least 5 years of experience in micro-architecture and RTL design.
• Proficiency with ASIC design tools such as Design Compiler, PrimeTime, ModelSim, etc.

Preferred Qualifications:

• Experience with mixed-signal IPs like SerDes, DDR, Die-to-Die links.
• Knowledge of low-power digital design.
• Experience developing automation tools in Python, Perl, or C.
• Support for mixed-signal design verification.

Additional Minimum Qualifications:

• Bachelor's degree with 4+ years, Master's with 3+ years, or PhD with 2+ years in relevant ASIC work.

Qualcomm is committed to equal opportunity employment and provides accommodations for individuals with disabilities upon request. For accommodations, contact [e-mail] or visit https://qualcomm.service-now.com/hrpublic?id=hr.

Note: Resumes submitted via staffing or recruiting agencies without prior authorization will not be accepted.

Qualcomm is an equal opportunity employer, considering all qualified applicants without discrimination.

Pay Range & Benefits:

$140,000 - $210,000 plus annual bonus and RSU grants. Benefits include comprehensive packages supporting work-life balance. Contact your recruiter for details.

For more information, visit Qualcomm Careers.