Digital ASIC Design Engineer for High-Speed Interfaces

Qualcomm; San Diego (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

An established industry player is seeking a skilled Digital ASIC Design Engineer to join their innovative team in San Diego. This role focuses on developing high-speed interfaces vital for cutting-edge AI/ML, computing, and automotive products. You will define and design advanced PHYs, collaborate on architecture, and optimize designs for performance and efficiency. With a strong emphasis on using the latest ASIC tools and methodologies, this position offers a unique opportunity to contribute to groundbreaking technologies in a dynamic and supportive environment.

Benefits

Bonuses

RSUs

Comprehensive benefits package

Qualifications

• 5+ years of experience in micro-architecture and RTL design.
• Proficiency with ASIC front-end design tools like Design Compiler.

Responsibilities

• Define high-speed interface PHYs and collaborate on architecture.
• Own RTL design, optimize for power, performance, and area.

Skills

Micro-architecture design

RTL design

ASIC front-end tools

Power optimization

Performance optimization

Area optimization

Debugging skills

Education

Master's in Electrical or Computer Engineering

Bachelor's in Science or Engineering

Tools

Design Compiler

PrimeTime

ModelSim

Python

Perl

C

Job description

Digital ASIC Design Engineer for High-Speed Interfaces

Join to apply for the Digital ASIC Design Engineer for High-Speed Interfaces role at Qualcomm.

Company

Qualcomm Technologies, Inc.

Job Area

Engineering Group > ASICS Engineering

Summary

Qualcomm's mixed-signal IP design team seeks experienced senior ASIC digital designers to develop high-speed interfaces, including SerDes, DDR, and Die-to-Die technologies, crucial for AI/ML, computing, and automotive products.

Location

San Diego only

Responsibilities

• Define standard and proprietary high-speed interface PHYs
• Collaborate on architecture of high-speed interfaces
• Design microarchitecture of IP blocks
• Own RTL design and implement specifications
• Optimize for power, performance, and area
• Utilize front-end ASIC design tools (lint, CDC, DFT, synthesis, FV, STA)
• Create design specifications and verification plans
• Coordinate with physical design team
• Define test plans, verify design, and debug bugs
• Support silicon bringup and debugging

Minimum Qualifications

• Master's in Electrical or Computer Engineering or related field
• 5+ years in micro-architecture and RTL design
• Proficiency with ASIC front-end tools (Design Compiler, PrimeTime, ModelSim, etc.)

Preferred Qualifications

• Experience with mixed-signal IPs (SerDes, DDR, Die-to-Die)
• Background in low-power digital design
• Experience with automation tools (Python, Perl, C)
• Support for mixed-signal verification

Additional Minimum Requirements

Bachelor's in Science or Engineering + 4+ years of ASIC experience, or Master's + 3+ years, or PhD + 2+ years.

Other Details

Salary: $140,000 - $210,000 plus bonuses, RSUs, and benefits. Equal opportunity employer. Location: San Diego only.