Digital ASIC Design Engineer

Remote; San Francisco (CA); Remote; USD 120,000 - 180,000; Full time

Job summary

AttoTude is seeking an experienced Digital IC Design Engineer to join a growing team focused on cutting-edge DSP and mixed-signal ICs. This hands-on role requires deep technical expertise and strong collaboration within a team of seasoned engineers to deliver tape-outs.

Minimum 5+ years in CMOS digital IC design with SystemVerilog, plus scripting skills (Tcl, Python, shell). Remote work with occasional Bay Area travel (<10%) is offered, aligning with project needs and milestones.

Qualifications

• 5+ years of hands-on CMOS digital IC design experience
• Strong SystemVerilog coding/verification
• Scripting: Tcl, Python, and shell
• Experience with PCIe, AXI, UCIe, SPI, I2C, and APB bus interfaces
• Excellent communication and teamwork skills

Responsibilities

• Translate flow requirements into architecture and design specs
• Collaborate with Systems Engineers for power, performance, area trade-offs
• Write RTL and SystemVerilog testbenches to verify designs
• Develop timing constraints, synthesize, STA, and timing closure
• Perform gate-level simulations and post-tapeout integration support
• Work with cross-functional teams to ensure on-time tape-outs
• Stay updated on high-speed IC design trends and methodologies
• Occasional Bay Area travel (<10%) for a remote role

Skills

SystemVerilog

CMOS design

Team collaboration

Communication

Education

Bachelors in Electrical Engineering

Master's in Electrical/Computer Engineering (preferred)

Tools

XCelium

Genus

Tempus

Conformal

Voltus

Job description

About the Role

We are seeking an experienced Digital IC Design Engineer to join our growing team. In this role, you will be part of an experienced design team developing cutting-edge DSP and mixed-signal ICs. This is a hands-on technical position that requires in-depth technical expertise, and the ability to work in a team of highly experienced engineers to accomplish the goals.

Key Responsibilities

• Flow system level requirements into Architecture and Design Specifications
• Work closely with Comm Systems Engineers to recommend implementation options for best power, performance, and area.
• Document and write RTL code to meet system requirements
• Write SystemVerilog testbenches and testcases to fully verify the design
• Develop timing constraints, Synthesize the design and perform Static Timing Analysis and Timing Closure.
• Perform gate level simulations.
• Support lab and HW/SW integration post-tapeout
• Collaborate with cross-functional teams to ensure timely project execution and design tape-outs
• Stay updated with the latest trends and technologies in wideband high speed IC design and apply them to improve project outcomes
• Occasional travel to the Bay Area (<10%) for remote position

Qualifications

Required

• 5+ years of hands-on experience in CMOS (bulk and FinFET), digital IC design in various process technologies
• Proven experience in strong coding/verification in SystemVerilog is required
• Scripting language experience: Tcl, Python, and shell scripts required.
• Bus interfaces: PCIe, AXI, UCIe, SPI, I2C, APB
• Strong communication and teamwork skills

Education

• Bachelor’s Degree in Electrical Engineering or related field is required
• Master’s Degree in Electrical Engineering, Computer Engineering or a related field is preferred

Preferred

• Experience designing high speed Modems, SerDes, DSP blocks, FFTs, clock recovery, carrier recovery, digital filters, CTLE, DFE and MLSE.
• Experience matching and debugging Matlab models and vectors in RTL/gate level simulations.
• Experience working on a multidisciplinary team with Systems, RF, Mixed Signal, and SW engineers
• Experience with Cadence tools: XCelium, Genus, Tempus, Conformal, and Voltus
• Experience delivering IP blocks to internal and external customers
• Ability to drive innovation and implement new design methodologies.

About Attotude

AttoTude is at the forefront of revolutionizing data centers through advanced interconnect technology based on wired THz transceivers. By adapting the fiber from photonics and advancing today's ASICs to THz, our innovative AttoEngine eliminates networking bottlenecks, enabling high-speed interconnects for AI data centers. We are committed to overcoming existing networking bottlenecks to unleash the full potential of artificial intelligence.

Why Join Us

Work at the forefront of semiconductor research and innovation in digital communications.

Collaborate with a multidisciplinary team driving the next generation of THz technology

Access to state-of-the-art tools and processes at the leading-edge of ASIC development.

Competitive compensation, professional growth, and opportunities for scientific contribution.