Design Verification Lead

Neurophos; Austin (TX); On-site; USD 190,000 - 260,000; Full time

Benefits offered by this job

Health premium coverage

HSA contributions

Unlimited PTO

401(k) matching

Stock options

Voluntary benefits package

Job summary

Neurophos, located in Austin, TX (onsite) with a niche in silicon photonics, seeks a seasoned Verification Architect to lead end‑to‑end verification of GPU-class/ASIC blocks. You will own testbench architecture, integrate VIPs, and drive emulation and tapeout readiness.

Join a fast‑growing AI hardware startup and shape the verification roadmap. You will coordinate across RTL, physical design, DFT and validation teams while leveraging AI tooling to accelerate coverage closure.

Qualifications

• 8 to 15 years in design verification, including leading verification on a GPU-class or complex compute ASIC through tapeout.
• Deep UVM and SystemVerilog expertise, including ownership of testbench architecture, formal verification, coverage analysis and CI/CD methodology.
• Gate-level simulation experience. You know what gate sim costs you in visibility and where it belongs in a tapeout schedule.
• Verification experience on a chip with many independently developed blocks and analog components, including integration of analog models.
• Comfort standing up a verification environment end to end, including emulation infrastructure.
• Breadth across the flow, from module-level simulation through SoC integration and into validation planning.

Responsibilities

• Own verification methodology and testbench architecture, built on UVM with a strong emphasis on AI driven flows.
• Build the verification plan across levels: module-level simulation, SoC integration, interface checks, top-level IO, and how each feeds the validation plan.
• Specify, evaluate and Integrate third party VIP into the environment Own gate-level simulation with SDF-annotated timing as part of tapeout closure.
• Extend our FPGA-based verification harness so modules can be exercised with real code, quickly, without burning simulator licenses.
• Stand up and operate our emulation environment, including provisioning and execution on cloud-hosted infrastructure.
• Use AI tooling to generate and iterate testbenches and assertions, optimizing based on coverage feedback, and iterating to ensure high quality verification.
• Build and lead the verification team, partnering with system architecture, RTL design, physical design, DFT and validation.

Skills

UVM / SystemVerilog

Gate-level verification

SoC verification

CI/CD

Emulation infrastructure

Team leadership

Analog model integration

Hands-on emulation

Cadence toolchain

FPGA verification

WREAL models

Tools

Palladium

Cadence toolchain

FPGA-based verification

WREAL

Job description

About Neurophos

The demand for new data centers and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck means rethinking the fundamental architecture of inference compute. The industry's current path can't meet the need, so we're taking a different approach.

Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.

We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others.

Join us and shape the future of computing!

Location: Austin, TX or Sunnyvale, CA. Full-time onsite position.

Reports To: Director of Digital Design

FLSA Status: Exempt

Key Responsibilities

• Own verification methodology and testbench architecture, built on UVM with a strong

  emphasis on AI driven flows.

• Build the verification plan across levels: module-level simulation, SoC integration,

  interface checks, top-level IO, and how each feeds the validation plan.

• Specify, evaluate and Integrate third party VIP into the environment

  Own gate-level simulation with SDF-annotated timing as part of tapeout closure.

• Extend our FPGA-based verification harness so modules can be exercised with real

  code, quickly, without burning simulator licenses.

• Stand up and operate our emulation environment, including provisioning and execution

  on cloud-hosted infrastructure.

• Use AI tooling to generate and iterate testbenches and assertions, optimizing based on

  coverage feedback, and iterating to ensure high quality verification.

• Build and lead the verification team, partnering with system architecture, RTL design,

  physical design, DFT and validation.

Qualifications

• 8 to 15 years in design verification, including leading verification on a GPU-class or

  complex compute ASIC through tapeout.

• Deep UVM and SystemVerilog expertise, including ownership of testbench architecture,

  formal verification, coverage analysis and CI/CD methodology.

• Gate-level simulation experience. You know what gate sim costs you in visibility and

  where it belongs in a tapeout schedule.

• Verification experience on a chip with many independently developed blocks and analog

  components, including integration of analog models.

• Comfort standing up a verification environment end to end, including emulation

  infrastructure.

• Breadth across the flow, from module-level simulation through SoC integration and into

  validation planning.

Preferred Skills

• Hands‑on emulation experience, Palladium or equivalent.

• Development of analog models using WREAL or equivalent descriptions

• FPGA-based verification or prototyping experience.

• Cadence toolchain experience.

• Experience using AI tooling to accelerate testbench development and coverage closure.

• Exposure to silicon photonics or optical component verification.

What We Offer

This is an opportunity to play a pivotal role in an innovative startup redefining the future of AI hardware. Work on game‑changing technology at the intersection of photonics and AI as part of a collaborative, brilliant team. You’ll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence. Come help us bring this transformative technology to the world.

Benefits

Join a team that invests in your future and your well‑being. At Neurophos, we offer:

• 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.

• Unlimited PTO. No rigid vacation banks, just a focus on delivery.

• 401(k) matching and stock option opportunities to ensure our success is your success.

• Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.

• Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don’t.