Design Verification Engineer - LEO Satellite ASICs

Amazon Kuiper Manufacturing Enterprises LLC; Austin (TX); On-site; USD 115,000 - 160,000; Full time

Job summary

Amazon Leo in Austin, TX is seeking a verification engineer to define and implement the digital chip SOC verification for low-earth orbit satellite communications using Verilog/SystemVerilog and UVM. The role emphasizes robust test environments and automated regression workflows.

The candidate should have a Bachelor's in Electrical/Communications Eng or CS and 2+ years in verification and UVM, with pluses for Matlab, SystemC, and modem verification experience.

Qualifications

• Bachelor's degree in Electrical/Communications Engineering or Computer Science, or equivalent experience.
• 2+ years in verification, preferably in communication systems.
• 2+ years in UVM.
• Master's or Ph.D. in Electrical/Communications Engineering is a plus.
• 3+ years in digital verification, preferably in communication systems.
• Familiarity with Matlab.
• Modem design verification experience.
• SystemC, C or Matlab model development or DV integration experience.
• Comfortable with AI-assisted tools to accelerate verification workflows.
• Familiarity with formal verification techniques.

Responsibilities

• Implement a state of the art verification environment to facilitate testing of the RTL against reference Matlab/C models.
• Develop detailed test plans and write tests, run regressions, collect coverage matrices and report progress to the program.
• Participate in the validation of ASIC implementations in Verilog/SystemVerilog.
• Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM.
• Develop a highly automated environment to run regressions that can be used to make builds and maintain organization of the database.

Skills

Verification

UVM

Matlab

SystemC

C

Education

Bachelor's degree in Electrical / Communications Engineering or Computer Science

Tools

Verilog

SystemVerilog

UVM

Matlab

Job description

Amazon Leo in Austin, TX is seeking a verification engineer to define and implement the digital chip SOC verification for low-earth orbit satellite communications using Verilog/SystemVerilog and UVM. The role emphasizes robust test environments and automated regression workflows.

The candidate should have a Bachelor's in Electrical/Communications Eng or CS and 2+ years in verification and UVM, with pluses for Matlab, SystemC, and modem verification experience.